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Virtula gate test

AnilGoudar asked in Digital Logic Oct 3, 2017

394 views

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Can somebody explain the question, please?

digital-logic
flip-flop

AnilGoudar asked in Digital Logic Oct 3, 2017

394 views

3 Comments

by Kaluti

commented Oct 4, 2017

is answer d

0

0

commented Oct 4, 2017 edited Oct 4, 2017 by Shubhanshu

how the output Y can be 1, as it is of the form Data.(Data)' which will always 0.

1

1

commented Oct 4, 2017

Ans given is A option

0

0

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1 Answer

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Option D is Correct ..becoz if we take I or 0 than both case final become Zero

Rackson answered Oct 7, 2017

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We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be: $\mathrm{T}=\mathrm{J}=\mathrm{K}$ $\text{T}=\text{JQ}^{\prime}+\text{K}^{\prime} Q$ $\text{T}=\text{JQ}^{\prime}+K Q$ $\text{T}=\text{JQ}+\text{KQ}'$

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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 52
Consider the sequential circuit shown below. Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transition diagram for the circuit above is shown in: a b c d

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GO Classes asked in Digital Logic Jan 13

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GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 39
The circuit shown below is designed using two multiplexers. This circuit is equivalent to: a positive edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\text{D}$ flip flop a positive edge triggered $\mathrm{D}$ flip flop

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admin asked in Digital Logic Feb 15, 2023

8,704 views

GATE CSE 2023 | Question: 33
Consider a sequential digital circuit consisting of $\mathrm{T}$ flip-flops and $\mathrm{D}$ flip-flops as shown in the figure. $\text{CLKIN}$ is the clock input to the circuit. At the beginning, $\text{Q1, Q2}$ and $\text{Q3}$ have values $0,1$ and $1,$ respectively. ... $\text{NEVER}$ be obtained with this digital circuit? $(0,0,1)$ $(1,0,0)$ $(1,0,1)$ $(1,1,1)$

admin asked in Digital Logic Feb 15, 2023

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