There they have clearly mentioned when clr is 1, it clears output to 0. In our case we don't have such information, the first thing that struck me when I trying to solve this problem we get clr 1 from state 0,1 .... and if I assume it will clear all output to 0 0 0 0 then, how my counter will increment hence the first thought was it is reversed, so I assumed that whenever it will be 0 it will reset input.
at 1 0 1 0 you get output from last Nand as zero and hence you reset the all output to 0 0 0 0. Sometimes it is difficult to recollect what we have learned, but then solving question logically should give you the right answer. When they give when clr is 1 then reset then no problem, when they don't mention anything assume it will reset at 0. In that question that might be a clr complement.
