Suppose that in 1000 memory references there are 150 misses in first level and 100 misses in second level cache. Assume that miss penalty from L2 cache to memory is 120 cycles. The hit time of L2 cache is 50 cycles.
If there are 4 memory references per instruction, the average stall per instruction is
Tavg stall/ints = Miss in L1/int * Hit in L2 + Miss in L2/int * Miss Penality in L2(memory access ) here 4 memory for 1 instruction so for 1000 memory = 1000/4 = 250 Miss in L1 = 150 Miss in L2 = 100 Hit time L2 = 50 Miss penalty L2 = 120 therefore Tavg stall/ints = $\frac{150}{250}$*50 + $\frac{100}{250}$*120 = 78
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