Mem stall cycles due to misses per instruction
=(Miss rate in L1) ∗(Miss penalty of L1)
= (Miss rate in L1) ∗(Total time of L2)
= (Miss rate in L1) ∗(Hit Time of L2 + Miss Time of L2)
= (Miss rate in L1) ∗(Hit Time of L2 + ( Miss Rate of L2 * Miss penalty of L2 ))
= (80/2000) * ( 30 + ( 40/80 * 200 ))
= (0.04) * ( 30 + ( 100 ))
= (0.04) * ( 130)
= 5.2 Clock cycles