Made Easy Test series

Question

Match List I (Characteristic) with List II (Processor Architechture) and select the correct answer using the code given below the lists:

List I                                                                                List II

(a) Micro-code for several instructions                                1. Both RISC and CISC

(b) Lack of indirect addressing                                           2. CISC only

© Presence of on-chip cache                                            3. Neither RISC nor CISC

(d) Simple optimizing compiler                                          4. RISC only

 

     A      B      C     D

(a) 2       4       1     3

(b)1        3       2     4

(c)2        3       1     4

(d)1        4       2    3

Comments

HeadShot

so on chip cache is present in both RISC and CISC architechture right?

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@Somoshree Datta 5 

Atleast It​​​ seems so from that context. 

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Indirect addressing is possible in CISC right?