MadeEasy Test Series: CO & Architecture - Cache Memory

Question

Comments

In solution they have considered

Miss ratio for L2 ==> 150 / 2000

But considering hierarchical structure ..it should be 150 / 320 ??

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yes...

I don't know why you post screenshot, is there any cause behind it ?

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..it takes time for typing and if wrong values typed whole discussion will get wrong ..

Sorry i will edit all such posts 👍

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if you edit your posts after discussion, then there is no problem, if you left them that lead to problem

Answer 1

26 clock cycles

Answer 2

L1 miss rate = 320/2000

L2 miss rate = 150/320

so EMAT = $1+ 320/2000(10 + 150/320(300))$ = 25.1 clock cycle