MadeEasy Test Series: CO & Architecture - Cache Memory

Question

 

A CPU has recorded 450 memory references. The CPU has been organized into 2-level of cache memory  L1 and L2 . There are 50 misses and 25 misses in L1 and L2 respectively. The miss penalty from L2 cache to memory is 60 cycles and hit time of L2 cache is 30 cycles. What is the average stall (in cycles) per instruction.?

1. 20
2. 40
3. 80
4. 32

Comments

@Shaik Masthan Could you please help!

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some data missing in the question ( Howmany memory references each instruction takes ? )

https://gateoverflow.in/91103/me-flt-4-q-58

still you have problem, then comment !

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@Shaik Masthan Thanks :)

Answer 1

option A is correct

no of stall stalls per memory access (memory reference)= Miss rate of L1 * Miss penalty of L1 +

                                                                Miss rate of L1 * Miss rate of L2 * Miss penalty of L2

=$(150/450)*30+((50/450)*(25/50))*60 =300/45$ stall

here 3 memory reference / instruction

so stall in one instructions=300*3/45=20

Comments

here 3 memory reference / instruction....how you got this?

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actually  it is madeeasy test series Q, and they given this thing in question last line, but asker forgot to write in the Q