Self Doubt

Question

When using pipelining can we have an arrangement like this?

I1	F1	D1	E1	M1	W1
I2		F2	______	____	_____	D2	E2	M2	W2
I3			F3	D3	E3	M3	W3

Where  I2 has Read after write dependency  on I1 and operand forwarding is not used.

I3 is independent of I1 and I2

F=INSTRUCTION FETCH.

D=DECODING AND READING THE OPERANDS FROM THE REGISTER

E=EXECUTE

M=MEMORY OPERATION

W=WRITE BACK

 

Comments

Why there are 3 stalls??

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We can do it.

  I2 has Read after write dependency  on I1

It means that I2 should read only after I1 writes i.e. after W1 D2 should happen.

However we can optimize and save 1 Clock cycle by executing I3 before I2 as I3 is independent of I1 and I2.

I1	F1	D1	E1	M1	W1
I3		F3	D3	E3	M3	W3
I2			F2	X	X	D2	E2	M2	W2

 

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we have to wait instruction 1 to write operand in memory so instruction 2 can access it in decode phase