There are two cases, first if $X_{in}=0$ and second if $X_{in}=1$ And its given that state of $X_{in}$ does not change in the middle of its working.
Case 1 : $X_{in}=0$
If one input of NAND gate is 0, then its output will be always 1. Hence in this case, $D_B$ would always receive $1$ as input. We should make truth table accordingly as below :
Clock |
$Q_B$ |
$Q_A$
|
$D_B=1$ |
$D_A=Q_A \bigoplus Q_B$
(calculated from previous states)
|
0 (initial) |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
2 |
1 |
1 |
1 |
0 |
3 |
1 |
0 |
1 |
1 |
4 |
1 |
1 |
|
|
We can see that the output $Q_BA_A$ "after a few clock cycles" is like 10-11-10-11 and so on. Only two states $10$ and $11$ are in cycle.
Now see the options B and D. Option B matches here. But still we will take case 2 also to check what happens :
Case 2 : $X_{in}=1$
If one input of NAND gate is 1, then its output will be compliment of other input. Hence in this case, $D_B$ would always receive $\bar{Q_A}$ as input. We should make truth table accordingly as below :
Clock |
$Q_B$ |
$Q_A$
|
$D_B=\bar{Q_A}$
(calculated from previous states)
|
$D_A=Q_A \bigoplus Q_B$
(calculated from previous states)
|
0 (initial) |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
2 |
1 |
1 |
0 |
0 |
3 |
0 |
0 |
1 |
0 |
4 |
1 |
0 |
1 |
1 |
5 |
1 |
1 |
0 |
0 |
6 |
0 |
0 |
|
|
We can see that the output $Q_BA_A$ 00-10-11-00-10-11 and so on. Three states $00$, $10$ and $11$ are in cycle.
Check the options A and C, Both are incorrect.
Hence considering both Cases, Correct answer is OPTION B.