GATE CSE 2016 Set 1 | Question: 31

Question

The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $\text{DMA}$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.

Comments

Data count register = $16$ bits.

=> Data that can be transferred at once = $2^{16}$ bytes. (Because byte addressable memory)

Total data to be transferred = $29154*1024$ bytes.

 

Number of transfers required = $29154*1024 \div 65536=455.531$

So, 456 attempts required.

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The mode(cycle stealing/burst) is not given explicitly. However, from what I have observed, devices which are relatively fast(like disk) are usually operated in burst mode while those that are relatively slow(like printer) are usually operated in cycle stealing mode.

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But still it is not compulsory.

It can work in cycle stealing mode we get ans : 0.

It can also work in transparent mode we can get ans : 1.

So all these answer should be correct right, since they haven’t written minimum or maximum?

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how much data DMA can transfer in one cycle??

I never heard of data count register. Can anybody share some reference?

Answer 1

Data count register gives the number of words the DMA can transfer in a single cycle..

Here it is $16$ bits.. so max $2^{16}$ words can be transferred in one cycle..

Since memory is byte addressable.. $1 \text{ word}=1\;\text{byte}$
                                                so $2^{16}$ bytes in $1$ cycle..
Now for the given file..
                               File size $=29154\ \textsf{KB} = 29154\times 2^{10}\ \textsf{B}$
                                                  $1$ cylce $\rightarrow$ DMA transfers $2^{16}\ \textsf{B}$
i.e 
                                             $1\ B$ transfered by DMA $\rightarrow \dfrac{1}{2^{16}}$ cycles.

Now, for full file of size $29154\ \textsf{KB},$

Minimum number of cylces $=\dfrac{(29154\times 2^{10}\ B)}{2^{16}}= 455.53$

But number of cylces is asked so $455.53\rightarrow 456.$

Comments

@cyril you are correct. $2^{16}-1$ is the highest unsigned value the register can represent and we can transfer that much amount (bytes) of data at max in one go..

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@Deepak Poonia Sir is @cyril’s comment “ I have this doubt because am told that out of 2^16 sequences, the sequence of all 0’s is used to represent that there is no data to be transferred and hence its not included.”  True??

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@abir_banerjee doubt resolved??

Answer 2

Size of data count register of the DMA controller = 16 bits

Data that can be transferred in one go = 2¹⁶ bytes = 64 kilobytes File size to be transferred = 29154 kilobytes.

So, number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory = ceil(29154/64) = 456  

Comments

c? There are no options:p. Correct answer btw:)

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Correct answer is 456 only.

Answer 3

minimum 456

Comments

An explanation would be helpful.

Answer 4

456 cycles