Recent questions and answers in CO & Architecture

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GATE2019-1.8

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GATE2019-4.8

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GATE2019-2.8

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GATE2019-3.8

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GATE2019-6.8

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GATE2019-7.8

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GATE2019-8.8

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GATE2019-9.8

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GATE2019-13.8

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GATE2019-15.8

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GATE2019-16.8

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17

GATEBOOK-2019 Grand Test COA-1
The Direct memory access based transfer is initiated by which of the following: Processor Kernel/library routine Device controller Running process

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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18

GATEBOOK-2019 Grand Test COA-2
A control unit of a processor can generate a maximum of $102$ control signals. It is known that to perform any instruction it needs at least 4 microinstructions on an average and any microinstruction needs at most three active control signals. What should be the width of control words in this control unit which can check a dozen of conditions :---

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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19

GATEBOOK-2019 Grand Test COA-3
To use the input and/or output of commands from/to files or join multiple commands together using pipes is known as: Pipelining Interfacing I/O redirection I/O chaining

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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20

GATEBOOK-2019 Grand Test COA-4
There are exactly M blocks in main memory which can be mapped to same cache sets. The cache is 4-associative and number of blocks in cache is 2L. The size of cache line is B words and word contains 16 bytes in it. The size of main memory in number of blocks, is: $2L*2^M$ $2^{\frac{M*L}{2}}$ $\frac{M*L}{2}$ $\frac{M*2*L}{4*16*B}$

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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21

GATEBOOK-2019 Grand Test COA-5
Assume that for a certain processor, a read request takes 50 nanoseconds on a cache miss and 5 nanoseconds on a cache hit. Suppose while running a program, it was observed that 80\% of the processor's read requests result in a cache hit. The average read access time in nanoseconds is: 12 14 18 22

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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22

GATEBOOK-2019 Grand Test COA-6
In a memory system the memory size is M bytes, a 4-way set associative cache size is C bytes and block size is B bytes. The number of set index bits is: $log\frac{M-4B}{C}-2$ $\frac{log C}{4B}+2$ $log{\frac{C}{4B}}-2$ $log{\frac{C}{B}}-2$

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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23

GATEBOOK-2019 Grand Test COA-7
A processor needs to transfer a file of 36 MBytes from disk to main memory. The memory is byte addressable. The size of the data count register of a DMA controller is 12 bits. The minimum number of times the DMA controller needs to get the control of the ... $T_B$. Then the minimum number of bits required to represent the value of the ratio $\frac{T_C}{T_B}$ is:---

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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24

GATEBOOK-2019 Grand Test COA-8
A CPU has 32-bit instructions. A program starts at address $2055_{10}$. Which one of the following (all in decimal) is a legal program counter: 3515 3516 3517 3518

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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25

GATEBOOK-2019 Grand Test COA-9
How many 8K X 4 ROM chips are needed in order to build a bigger chip whose size is 2 MBytes. 64 128 256 512

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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26

GATEBOOK-2019 Grand Test COA-10
A processor, that has sign, overflow and carry flag bits as most significant three bits (in that order) of its 8 bit program status word (PSW), performs addition of the following two 2's complement 8 bit numbers 01101011 and 00110110. If after the ... performed, the least 5 bits have a octal equivalent as 16, the decimal representation of the PSW is:: 216 28 56 78

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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27

GATEBOOK-2019 Grand Test COA-11
There are two organizations of caches with same values of memory size 64Mbytes, cache size 16Kbytes and block size 64bytes, as follows: (i) A 4-way set associative (ii) A full associative cache The number of Tag-comparators used in (i) is $C_1$ with input size of $T_1$ and ... size of $T_2$ . Let $D=|T_2-T_1|$ and $R=\frac{C_2}{C_1}$. The value of $D*R$ is:---

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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28

GATEBOOK-2019 Grand Test COA-12
The two different organizations a and b of 5 stage processor having following latencies (in ps): ... 220, 1/780) (570, 570 ,1/1700) , (220, 780, 1/780) (570, 1700, 1/570), (220, 780, 1/220)

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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29

GATEBOOK-2019 Grand Test COA-13
A computer has a 512 kBytes, 16-way set associative, write back data cache with block size of 64 bytes. The processor sends 64 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, a modified bit and a replacement bit and 2 more control bits. The size of the cache tag directory in KBytes is:---

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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30

GATEBOOK-2019 Grand Test COA-14
Consider a two-level cache hierarchy with $L_1$, $L_2$ and $L_3$ caches. An application incurs 2.5 memory accesses per instruction on average. For this application, the miss rate of $L_1$ cache is 0.15; the $L_2$ cache experiences, on ... 1000 instructions. What is the percentage of total references which needs to access main memory? 0.6875 0.4667 0.8000 1.375

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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31

GATEBOOK-2019 Grand Test COA-15
Consider a machine with a byte addressable main memory of 16 Mbytes. Assume that a direct mapped data cache of 64 blocks with block size of 256 bytes is used in the system. A 150 x 150 two-dimensional array with element size of 1 byte is stored ... of the data cache do not change in between the two accesses. How many data misses will occur in total? 280 240 148 184

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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32

GATEBOOK-2019 Grand Test COA-16
A machine has a 32-bit architecture, with three-word long instructions. It has 6400 General Purpose Registers and 810 Special Purpose Registers, each of which is 32-bits long. It needs to support 1670 different instructions, which have an ... immediate operand is represented in 2's complement integer format, the maximum positive value of the immediate operand is:---

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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33

GATEBOOK-2019 Grand Test COA-17
Consider the following one address instructions for a hypothetical processor implementing a function denoted by $f$: Move x Mult x Store z Move x Mult 2 Add z Add 3 Store y Which of the following values represents the value of the function for input value = $(17)_{10}$?

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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34

GATEBOOK-2019 Grand Test COA-18
Consider two different designs of ALU as follows: (i) A part of a bigger task is improved twenty times than it was before. The other part of the same task constitutes 60\% of the overall task time and it remains unchanged. (ii) The ... value is the best approximate difference between the two speedups achieved in those two improvements: 0.3567 0.2667 0.4875 0.4325

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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35

GATEBOOK-2019 Grand Test COA-19
Arrange the following configuration for CPU in decreasing order of operating speeds: Hard wired control, Vertical microprogramming, Horizontal microprogramming. Hard wired control, Vertical microprogramming, Horizontal microprogramming. ... , Vertical microprogramming, Hard wired control. Vertical microprogramming, Horizontal microprogramming, Hard wired control.

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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36

GATEBOOK-2019 Grand Test COA-20
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. ... dependencies in the sequence of instructions are, respectively, 5, 2, 3 4, 2, 2 6, 3, 3 8, 8, 3

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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37

GATEBOOK-2019 Grand Test COA-21
Consider a 32-bit processor with 150 registers and having 76 different types of instructions. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a thirteen-bit immediate value. Each ... a program has 1000 instructions, the amount of memory (in bytes) consumed by the program text is:---

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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38

GATEBOOK-2019 Grand Test COA-22
A hard disk with a transfer rate of 500 Mbits per second is constantly transferring data to memory using DMA. The processor is running effectively at half of its maximum frequency of 1GHz. To initiate a DMA transfer it takes 70 CPU cycles and for taking back ... to the last time control of the BUS is revoked from DMA controller: 7.4500 ms 9.3850 ms 11.6745 ms None

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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39

GATEBOOK-2019 Grand Test COA-23
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, ... loop and no two iterations of the loop can be overlapped. The time (in ns) needed to complete the program is:---

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

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40

GATEBOOK-2019 Grand Test COA-24
Consider a CPU that executes the following mix of instructions: 43\% are ALU operations that take 1 Cycle 21\% are Load instructions that take 1 Cycle 12\% are Store instructions that take 2 Cycles 24\% are Jump instructions that take 2 Cycles A ... takes 10\% less time with changes. CPU takes 5\% more time with changes. CPU takes 7\% more time with changes.

answered Jan 8 in CO & Architecture by GATEBOOK Loyal (7.7k points) 1 view

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

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