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Recent questions and answers in CO & Architecture
0
votes
2
answers
1
Carl hamacher
A program consists of two nested loops-a small inner loop and a much larger outer loop.The decimal memory addresses shown delineate the location of the two loops and the beginning and end of the total program. All memory locations in the various sections of ... the cycle time of the cache is 1τ s. Compute the total time needed for instruction fetching during execution of the program.
answered
May 21
in
CO & Architecture
by
isilia
(
11
points)
|
202
views
co-and-architecture
carl-hamacher
cache-memory
0
votes
0
answers
2
PIPELINING.
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?
asked
May 21
in
CO & Architecture
by
Ritabrata Dey
(
41
points)
|
3
views
#computer
co-and-architecture
+43
votes
3
answers
3
GATE2004-63
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ \begin{array}{|l|l|c|} \hline \text {Instruction} & \text{Operation }& \text{Instruction size} \\&& \text{(in words)} \\\ ... halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be $1007$ $1020$ $1024$ $1028$
answered
May 21
in
CO & Architecture
by
Apoorv Singh
(
11
points)
|
8.1k
views
gate2004
co-and-architecture
machine-instructions
normal
0
votes
0
answers
4
Made Easy Test Series:Microprogramming
A hypothetical cpu supports $300$ instructions.each instruction takes $5$ cycle to accomplish the execution. the control unit is designed using vertical programming which has $130$ control signals $,64$ flags and $12$ branch conditions .$X$ and ... register$(CDR)$ respectively.value of $X+Y$ is ______? How to work with branch condition in micro programming :(
asked
May 20
in
CO & Architecture
by
srestha
Veteran
(
114k
points)
|
13
views
made-easy-test-series
microprogramming
co-and-architecture
0
votes
0
answers
5
ROM(self doubts)
The minimum size of the ROM which maintains truth table of square of 3 bit numbers is __________ (in bits)
asked
May 19
in
CO & Architecture
by
altamash
(
483
points)
|
10
views
+2
votes
1
answer
6
Cache Average access time
So as we know there are 2 different approaches for cache.. Sequential and the Hierarchical. Exactly which formula should I use when only access times and hit ratio is mentioned in case of 2 level memory system..? It would be great if someone explains how to approach questions related to average access time.
answered
May 19
in
CO & Architecture
by
Hirak
Active
(
2k
points)
|
104
views
cache-memory
co-and-architecture
0
votes
2
answers
7
Direct Mapped Cache Multiplexer
Is there any multiplexer(s) present in the implementation of Direct Mapped Cache? If yes, then the Hit latency would be Multiplexer latency + Comparator Latency?
answered
May 17
in
CO & Architecture
by
!KARAN
Active
(
1.8k
points)
|
65
views
icache-memory
direct-mapping
0
votes
0
answers
8
set associative (carl hamacher)
Block set associative cache consists of a total of 64blocks divided into 4blocks sets .The main memory contains 4096blocks ,each consisting of 128 words. how many bits for Main memory how many bits for TAG,SET,WORD . solution: MM=block size*words 2^12 * 2^7=19 bits TAG=9 SET=4 WORD=6 is this correct method or not please correct me
asked
May 13
in
CO & Architecture
by
altamash
(
483
points)
|
16
views
0
votes
0
answers
9
No of chips
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. No of chips required to design the memory system ______. Please provide a detailed solution.
asked
May 7
in
CO & Architecture
by
Tuhin Dutta
Loyal
(
9.6k
points)
|
32
views
co-and-architecture
memory-interfacing
chips
+3
votes
3
answers
10
UGCNET-June2016-III-5
The ____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. Base indexed Base indexed plus displacement Indexed Displacement
answered
May 7
in
CO & Architecture
by
Kuljeet Shan
Active
(
1.3k
points)
|
1.4k
views
ugcnetjune2016iii
co-and-architecture
addressing-modes
0
votes
0
answers
11
NTA NET DEC 2018-53
The decimal floating point number -40.1 represented using IEEE-754 32-bit representation and written in hexadecimal form is- 0xC2006000 0xC2006666 0xC2206000 0xC2206666
asked
May 7
in
CO & Architecture
by
Kuljeet Shan
Active
(
1.3k
points)
|
36
views
#ieee-representation
#floating-point-representation
+20
votes
3
answers
12
GATE2006-IT-40
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ respectively before the following program is executed. $\begin{array}{ll} \text{MOVI} & \text{$R_s, 1$} && \text{; Move immediate} \\ \text{LOAD} & \text{$R_d ... $20$ Memory location $1020$ has value $20$ Memory location $1021$ has value $20$ Memory location $1001$ has value $20$
answered
Apr 29
in
CO & Architecture
by
Sambhrant Maurya
Active
(
1.7k
points)
|
2.4k
views
gate2006-it
co-and-architecture
addressing-modes
normal
0
votes
1
answer
13
IIIT PGEE 2019
Which part in 8086 microprocessor is responsible for fetching instructions into the queue? BIU EU Stack Registers
answered
Apr 29
in
CO & Architecture
by
gaurav1.yuva
(
403
points)
|
60
views
iiith-pgee
8086
microprocessors
0
votes
0
answers
14
Branch Address
To get branch address, do we need base register value or Program Counter value?
asked
Apr 17
in
CO & Architecture
by
srestha
Veteran
(
114k
points)
|
43
views
co-and-architecture
0
votes
1
answer
15
which book should i refer to cover all the concept of cache memory and memory hierarchy in CO and Architecture.
answered
Apr 17
in
CO & Architecture
by
rajabhardwajrai
(
15
points)
|
67
views
0
votes
0
answers
16
#Pipeliningdoubt
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.
asked
Apr 16
in
CO & Architecture
by
Ritabrata Dey
(
41
points)
|
22
views
co-and-architecture
0
votes
0
answers
17
Goldman Sachs Screening Test
In Matrix Multiplication Operation Code uses Temporal Locality and Data uses Spatial Locality Data uses Temporal Locality and Code uses Spatial Locality Both data and code uses Spatial Locality Both data and code uses Temporal Locality
asked
Apr 14
in
CO & Architecture
by
ved
(
9
points)
|
15
views
0
votes
0
answers
18
Microprogrammed approach
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?
asked
Apr 12
in
CO & Architecture
by
Miny
(
149
points)
|
5
views
co-and-architecture
+14
votes
3
answers
19
GATE2015-2-24
Assume that for a certain processor, a read request takes $50$ $nanoseconds$ on a cache miss and $5$ $nanoseconds$ on a cache hit. Suppose while running a program, it was observed that $80$% of the processor's read requests result in a cache hit. The average read access time in nanoseconds is _____.
answered
Apr 9
in
CO & Architecture
by
Rishi yadav
Boss
(
11k
points)
|
3.5k
views
gate2015-2
co-and-architecture
cache-memory
easy
numerical-answers
+24
votes
4
answers
20
GATE2008-IT-38
Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address ... back to the stack. ADD (X)−, (X) ADD (X), (X)− ADD −(X), (X)+ ADD −(X), (X)
answered
Apr 7
in
CO & Architecture
by
Divy Kala
Junior
(
681
points)
|
2.7k
views
gate2008-it
co-and-architecture
machine-instructions
normal
+28
votes
5
answers
21
GATE2008-72
Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR[1024][1024]; int i, j; /* ... elements have the same cache index as $ARR[0][0]$? $ARR[0][4]$ $ARR[4][0]$ $ARR[0][5]$ $ARR[5][0]$
answered
Apr 5
in
CO & Architecture
by
Piyush ####
(
77
points)
|
3.2k
views
gate2008
co-and-architecture
cache-memory
normal
+1
vote
3
answers
22
Madeeasy Test Series
Suppose that in 1000 memory references there are 150 misses in first level and 100 misses in second level cache. Assume that miss penalty from L2 cache to memory is 120 cycles. The hit time of L2 cache is 50 cycles. If there are 4 memory references per instruction, the average stall per instruction is
answered
Apr 5
in
CO & Architecture
by
Sahil Arora
(
27
points)
|
666
views
+2
votes
1
answer
23
average memory access time
The access time of cache memory is 45 nsec and that of main memory is 750 nsec. It is found that 75% of memory requests are for read and remaining for write. If the hit access for read is 0.9 and hit ratio for write is 1 and write through protocol is used, then the average memory access time is ________.
answered
Apr 2
in
CO & Architecture
by
Hiral Rajgor
(
17
points)
|
423
views
cache-memory
+1
vote
6
answers
24
GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits
answered
Apr 2
in
CO & Architecture
by
Àbhíjèét Míshrà
(
47
points)
|
3.3k
views
gate2019
co-and-architecture
cache-memory
0
votes
0
answers
25
Carl Hamacher: Machine Instruction and Programs-Chapter $2$
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ ... //Auto Decrement $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement
asked
Apr 2
in
CO & Architecture
by
srestha
Veteran
(
114k
points)
|
39
views
co-and-architecture
carl-hamacher
0
votes
1
answer
26
Memory Access Doubt
How many memory accesses are there in this code? LOAD R1, a(RO)
answered
Apr 1
in
CO & Architecture
by
abhishekmehta4u
Boss
(
33.6k
points)
|
65
views
effective-memory-access
co-and-architecture
+2
votes
2
answers
27
MadeEasy Subject Test 2019: CO & Architecture - Pipelining
Consider a 5 stage pipeline with Instruction Fetch(IF),Instruction decode(ID),Execute(EX),Write back(WB),and Memory access(MA) having latencies(in ns) 3,8,5,6 and 4 respectively. What is average CPI of NON-PIPELINE CPU when speedup achieved by pipelined processor is 4?
answered
Mar 30
in
CO & Architecture
by
abhishekmehta4u
Boss
(
33.6k
points)
|
401
views
made-easy-test-series
co-and-architecture
pipelining
+1
vote
1
answer
28
Allen Career Institute:Computer Organization -Memory
The size of instruction in a single accumulator CPU organization is $16$ bits. In order to evaluate the expressions given below. How much memory space (bytes) is required for storing the program? evaluate the expression from left to right). Expression : $y=\frac{A-B+C}{E+F}$
answered
Mar 30
in
CO & Architecture
by
abhishekmehta4u
Boss
(
33.6k
points)
|
42
views
computer-organisation
+38
votes
4
answers
29
GATE2000-12
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is completed. ... and 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.
answered
Mar 23
in
CO & Architecture
by
abhishekmehta4u
Boss
(
33.6k
points)
|
4.5k
views
gate2000
co-and-architecture
pipelining
normal
descriptive
0
votes
0
answers
30
self-doubt
How do we perform 0 – 1 in 2’s complement subtraction using 1-bit register??
asked
Mar 21
in
CO & Architecture
by
Doraemon
(
203
points)
|
20
views
number-system
0
votes
0
answers
31
CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.
asked
Mar 20
in
CO & Architecture
by
Devshree Dubey
Boss
(
14k
points)
|
21
views
cpu
co-and-architecture
0
votes
0
answers
32
Subject Topic- CO & Architecture
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB
asked
Mar 18
in
CO & Architecture
by
Doraemon
(
203
points)
|
28
views
co-and-architecture
pipelining
0
votes
1
answer
33
GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.
answered
Mar 17
in
CO & Architecture
by
Anuranjan
(
61
points)
|
49
views
co-and-architecture
cache-memory
0
votes
1
answer
34
Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>set associative cache
answered
Mar 17
in
CO & Architecture
by
Anuranjan
(
61
points)
|
45
views
cache-memory
0
votes
0
answers
35
Self-doubt
How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)
asked
Mar 17
in
CO & Architecture
by
Anuranjan
(
61
points)
|
15
views
0
votes
0
answers
36
Cache Memory and Arrays
Can someone please provide a link to an article or a video explaining cache and arrays concept. Im having a hard time understanding that concept.
asked
Mar 16
in
CO & Architecture
by
amitqy
Active
(
1.9k
points)
|
14
views
0
votes
0
answers
37
Self-doubt
What is actually meant by average access time experienced by processor?
asked
Mar 14
in
CO & Architecture
by
Anuranjan
(
61
points)
|
14
views
+1
vote
2
answers
38
Gateforum Test Series: Databases - Indexing
suppose that in a file organization record size(R)=150 bytes , block size (B)=512 bytes. there are totally 30000 records. the data field on which indexing is done is 9 bytes and block pointer size is 7 bytes how many block access will be needed to access a data item in case of single level primary indexing?
answered
Mar 14
in
CO & Architecture
by
abhishekmehta4u
Boss
(
33.6k
points)
|
73
views
gateforum-test-series
databases
indexing
+1
vote
1
answer
39
Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .
answered
Mar 13
in
CO & Architecture
by
Debdeep1998
Junior
(
635
points)
|
46
views
pipelining
operand-forwarding
+1
vote
1
answer
40
Self-doubt
What is meant by cache index? Please state by example.
answered
Mar 13
in
CO & Architecture
by
Debdeep1998
Junior
(
635
points)
|
43
views
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