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A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
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121
UGC NET CSE | October 2020 | Part 2 | Question: 5
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
go_editor
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CO and Architecture
Nov 20, 2020
by
go_editor
3.5k
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ugcnetcse-oct2020-paper2
co-and-architecture
cache-memory
1
vote
2
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122
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 22
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
admin
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in
CO and Architecture
Apr 1, 2020
by
admin
1.8k
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nielit2017oct-assistanta-it
co-and-architecture
cache-memory
1
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123
NIELIT 2017 DEC Scientific Assistant A - Section B: 56
In a particular system it is observed that, the cache performance gets improved as a result of increasing the block size of the cache. The primary reason behind this is : Programs exhibits temporal locality Programs have small working set Read operation is frequently required rather than write operation Programs exhibits spatial locality
admin
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in
Operating System
Mar 31, 2020
by
admin
1.9k
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nielit2017dec-assistanta
operating-system
cache-memory
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3
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124
NIELIT 2016 DEC Scientist B (CS) - Section B: 37
The principle of locality of reference justifies the use of Non reusable Cache memory Virtual memory None of the above
admin
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in
Operating System
Mar 31, 2020
by
admin
1.0k
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nielit2016dec-scientistb-cs
operating-system
cache-memory
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4
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125
NIELIT 2017 DEC Scientist B - Section B: 4
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
admin
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in
CO and Architecture
Mar 30, 2020
by
admin
1.6k
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nielit2017dec-scientistb
co-and-architecture
cache-memory
1
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126
NIELIT 2017 DEC Scientist B - Section B: 16
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit
admin
asked
in
Operating System
Mar 30, 2020
by
admin
3.2k
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nielit2017dec-scientistb
operating-system
memory-management
paging
cache-memory
18
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127
GATE CSE 2020 | Question: 21
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2$0 ns to bring the first word of a block from the main memory, while ... word takes $5$ ns. The word size is $64$ bits. The average memory access time in ns (round off to $1$ decimal place) is______.
Arjun
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in
CO and Architecture
Feb 12, 2020
by
Arjun
15.5k
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gatecse-2020
numerical-answers
co-and-architecture
cache-memory
1-mark
21
votes
3
answers
128
GATE CSE 2020 | Question: 30
A computer system with a word length of $32$ bits has a $16$ MB byte- addressable main memory and a $64$ KB, $4$-way set associative cache memory with a block size of $256$ ... set. $A3$ and $A4$ are mapped to the same cache set. $A1$ and $A3$ are mapped to the same cache set.
Arjun
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in
CO and Architecture
Feb 12, 2020
by
Arjun
16.2k
views
gatecse-2020
co-and-architecture
cache-memory
2-marks
7
votes
5
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129
ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits
Satbir
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in
CO and Architecture
Jan 13, 2020
by
Satbir
6.0k
views
isro-2020
co-and-architecture
cache-memory
direct-mapping
normal
2
votes
3
answers
130
ISRO2020-43
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
Satbir
asked
in
CO and Architecture
Jan 13, 2020
by
Satbir
3.7k
views
isro-2020
co-and-architecture
cache-memory
normal
0
votes
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131
Andrew S. Tanenbaum (OS) Edition 4 Exercise 4 Question 32 (Page No. 335)
The performance of a file system depends upon the cache hit rate (fraction of blocks found in the cache). If it takes $1\: msec$ to satisfy a request from the cache, but $40\: msec$ to satisfy a request if a disk read is needed ... request if the hit rate is $h.$ Plot this function for values of $h$ varying from $0$ to $1.0.$
admin
asked
in
Operating System
Oct 27, 2019
by
admin
323
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tanenbaum
operating-system
file-system
cache-memory
descriptive
1
vote
0
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132
Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 10 (Page No. 174)
In the text it was stated that the model of Fig. $2-11(a)$ was not suited to a file server using a cache in memory. Why not? Could each process have its own cache?
admin
asked
in
Operating System
Oct 24, 2019
by
admin
341
views
tanenbaum
operating-system
process-and-threads
cache-memory
descriptive
0
votes
2
answers
133
Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 4 (Page No. 81)
To use cache memory, main memory is divided into cache lines, typically $32$ or $64$ bytes long. An entire cache line is cached at once. What is the advantage of caching an entire line instead of a single byte or word at a time?
admin
asked
in
Operating System
Oct 20, 2019
by
admin
1.0k
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tanenbaum
operating-system
cache-memory
descriptive
1
vote
1
answer
134
WEST BENGAL SET COMPUTER SCIENCE
A CPU has 32 bit-memory address and eacch word has size of 1 byte.
Jit Saha 1
asked
in
CO and Architecture
Sep 22, 2019
by
Jit Saha 1
449
views
co-and-architecture
cache-memory
0
votes
0
answers
135
set associative (carl hamacher)
Block set associative cache consists of a total of 64blocks divided into 4blocks sets .The main memory contains 4096blocks ,each consisting of 128 words. how many bits for Main memory how many bits for TAG,SET,WORD . solution: MM=block size*words 2^12 * 2^7=19 bits TAG=9 SET=4 WORD=6 is this correct method or not please correct me
altamash
asked
in
CO and Architecture
May 13, 2019
by
altamash
465
views
co-and-architecture
cache-memory
0
votes
1
answer
136
Self-doubt
How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)
Anuranjan
asked
in
CO and Architecture
Mar 17, 2019
by
Anuranjan
245
views
co-and-architecture
cache-memory
hit-ratio
array
0
votes
0
answers
137
Cache Memory and Arrays
Can someone please provide a link to an article or a video explaining cache and arrays concept. Im having a hard time understanding that concept.
amitqy
asked
in
CO and Architecture
Mar 16, 2019
by
amitqy
296
views
co-and-architecture
cache-memory
array
1
vote
1
answer
138
Self-doubt
What is meant by cache index? Please state by example.
Anuranjan
asked
in
CO and Architecture
Mar 13, 2019
by
Anuranjan
263
views
co-and-architecture
cache-memory
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