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A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
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31
Cache Mapping
In a 2 level hierarchy, the cache has an access time of 15 ns and the main memory has an access time of 110 ns, the hit rate of the cache is 90%. If the block size of the cache is 16 Bytes, then average memory access time including miss penalty is?
Mrityudoot
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in
CO and Architecture
Jun 5, 2023
by
Mrityudoot
616
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co-and-architecture
cache-memory
multilevel-cache
12
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4
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32
GATE CSE 2023 | Question: 54
An $8$-way set associative cache of size $64 \mathrm{~KB} \;(1 \mathrm{~KB}=1024\; \text{bytes})$ is used in a system with $32$-bit address. The address is sub-divided into $\text{TAG, INDEX},$ and $\text{BLOCK OFFSET.}$ The number of bits in the $\text{TAG}$ is ___________.
admin
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CO and Architecture
Feb 15, 2023
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admin
11.1k
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gatecse-2023
co-and-architecture
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numerical-answers
2-marks
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1
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33
#COA #CacheMemory
What is the default access method of Cache Memory? Simultaneous or Hierarchical?
iamsubhrajit
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in
CO and Architecture
Dec 31, 2022
by
iamsubhrajit
395
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co-and-architecture
cache-memory
2
votes
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34
cache miss question
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?
h4kr
asked
in
CO and Architecture
Dec 27, 2022
by
h4kr
535
views
co-and-architecture
cache-memory
multilevel-cache
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