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A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
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481
[COA] Hamacher Example 5.2,Page 322,Fifth edition
Writing the example in short words; Cache Access =1ns Main Memory Access =10 clock cycles Time to load word into the cache = 17 cycles 30% Instructions perform Memory read and write. Instruction cache Hit rate=.95 and Data cache ... same for both read and write access. Find the performance gain if we use system with cache over system without cache.
rahul sharma 5
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CO and Architecture
May 29, 2017
by
rahul sharma 5
618
views
co-and-architecture
cache-memory
1
vote
1
answer
482
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 29
Suppose in a system we store data using arrays, we have $2$ arrays A1 and A2. Array A1 contains $256$ elements of size $4$ bytes each. The first element is stored at physical address $4096$ ... of bytes that will be written to memory during execution of the loop is : $256$ $1$ $0$ $2048$
Bikram
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in
CO and Architecture
May 27, 2017
by
Bikram
530
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tbb-coa-2
co-and-architecture
cache-memory
0
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2
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483
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 27
Consider a memory hierarchy system consisting of two levels. The access time of level $1$ is $2$ ns. The miss penalty (The time to get data from level $2$, in case of miss) is $100$ ns. If the average memory ... the average access time to $40 \%$, the probability that valid data found in level $1$ is ___________ $\%$
Bikram
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in
CO and Architecture
May 27, 2017
by
Bikram
386
views
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
2
votes
2
answers
484
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 25
Suppose there are $500$ memory references in which $50$ misses in the $1$st level cache and $20$ misses in the $2$nd level cache . Let the miss penalty from L2 cache to memory is $100$ cycles. ... cycles. If there are $2.5$ memory reference/instruction , average number of stall cycles per instruction will be __________
Bikram
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CO and Architecture
May 27, 2017
by
Bikram
583
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tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
0
votes
2
answers
485
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 23
Consider a two level memory hierarchy having only one level cache and main memory. Cache and Main memory access times are $20$ ns and $120$ ns/word respectively. The size of cache block is $4$ words . If main memory is referenced $40 \%$ of the times, then average access time is _______ ns
Bikram
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CO and Architecture
May 27, 2017
by
Bikram
525
views
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
1
vote
1
answer
486
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 22
Suppose that a direct-mapped cache has $2^{10}$ cache lines, with $2^4$ bytes of data per cache line. If the cache is used to store blocks for a byte addressable memory of size $2^{30}$ bytes, then number of bytes of space will be required for storing the tags is ________ (put the integer value)
Bikram
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CO and Architecture
May 27, 2017
by
Bikram
285
views
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
0
votes
1
answer
487
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 16
Consider the following statements about the Locality of Reference principle used in the computer memory systems. The principal states that an already accessed memory location is accessed further again and it is also more likely that ... the above statements is/are TRUE? I only II only II and III only I and III only
Bikram
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CO and Architecture
May 27, 2017
by
Bikram
265
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tbb-coa-2
co-and-architecture
cache-memory
0
votes
4
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488
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 15
Consider a $2$ - way set associative cache memory with $4$ sets and total $8$ cache blocks $(0 - 7)$. Main memory has $64$ blocks $(0 - 63)$. If LRU policy is used for replacement and cache is initially empty then total number of conflict cache ... block references is: $0 \ 5 \ 9 \ 13 \ 7 \ 0 \ 15 \ 25$ $2$ $3$ $0$ $1$
Bikram
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CO and Architecture
May 27, 2017
by
Bikram
878
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tbb-coa-2
co-and-architecture
cache-memory
conflict-misses
0
votes
1
answer
489
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 12
A $4$ way set associative cache with a size of $32$ KB has line size $16$ Bytes. There is a Byte addressable main memory with a size of $256$ MB, then which of the following Main Memory block is mapped on to the set $'0'$ of Cache Memory? $(FCEE90B)16$ $(FECF10C)16$ $(CFEE09B)16$ $(CDDE00B)16$
Bikram
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in
CO and Architecture
May 27, 2017
by
Bikram
317
views
tbb-coa-2
co-and-architecture
cache-memory
0
votes
1
answer
490
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 8
A two-dimensional array int $a [32] [32]$ where each element takes $2$ byte, cache size $2^{12}$ bytes and line size is $2^6$ bytes. The following program segment is stored in the direct mapped cache. ... ][ j] = 0 If initially cache is empty then total number of compulsory cache miss for storing above array is ________
Bikram
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in
CO and Architecture
May 27, 2017
by
Bikram
372
views
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
1
vote
2
answers
491
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 7
A system is having $4$ way set associative cache of $256$ KB. The cache line size is $8$ words and each word has $32$ bits. Suppose memory addresses are $64$ bits long. Then number of bits required for the index field of the cache memory is _______
Bikram
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CO and Architecture
May 27, 2017
by
Bikram
635
views
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
0
votes
1
answer
492
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 4
Consider a computer system that has a cache with $512$ blocks, each of which can store $32$ bytes of data. All addresses are byte addresses.Then to which cache line will the memory address OXFBFC map to if the cache is direct mapped and ... respectively? $\text{DBA, 3C}$ $\text{1DA, 1D}$ $\text{1DF, 1F}$ $\text{1CF, 3E}$
Bikram
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in
CO and Architecture
May 27, 2017
by
Bikram
263
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tbb-coa-2
co-and-architecture
cache-memory
1
vote
1
answer
493
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 2
$16$kB cache with line size $64$B uses $4$ – way set associative mapping. Main memory is $8$ MB and byte addressable. The size of extra space needed for storing tag information in bytes is _________
Bikram
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in
CO and Architecture
May 27, 2017
by
Bikram
343
views
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
0
votes
1
answer
494
[COA] Cache terminology definitions
Please give definition for:- 1. Principle of inclusion 2. Cache coherence
rahul sharma 5
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in
CO and Architecture
May 26, 2017
by
rahul sharma 5
358
views
co-and-architecture
cache-memory
0
votes
0
answers
495
[COA] Cache Set associative mapping
Question 1:- Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different ... of bits taken were 6 ? How can i identify whether we need to convert to byte addressable from word size or not?
rahul sharma 5
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in
CO and Architecture
May 24, 2017
by
rahul sharma 5
1.1k
views
co-and-architecture
cache-memory
memory-interfacing
1
vote
1
answer
496
Hamacher COA 5.7,p-362
A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four 16-bit words, and each word has an associated 13-bit tag, as shown in Figure P5.2a. When a miss occurs during a read operation, the ... the cache is $1\tau$. Calculate the execution time for each pass. Ignore the time taken by the processor between memory cycles.
rahul sharma 5
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in
CO and Architecture
May 23, 2017
by
rahul sharma 5
955
views
co-and-architecture
cache-memory
secondary-storage
0
votes
3
answers
497
[COA][ Hamacher 1.6] Cache memory
1.6 Suppose that execution time for a program is directly proportional to instruction access time and that access to an instruction in the cache is 20 times faster than access to an instruction in the main memory. Assume that a requested instruction ... added only one then please explain why? part B) Does doubling cache means access time of cache is also doubled?
rahul sharma 5
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in
CO and Architecture
May 22, 2017
by
rahul sharma 5
1.8k
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co-and-architecture
memory-interfacing
cache-memory
1
vote
1
answer
498
[COA] Cache write through in hierarchical design
For hierarchical access and write-through,The average write time is given by: 1. Twt=H×Tmemory+(1−H)×(Tcache+Tmemory) 2. Twt=Tmemory Which one to refer in question?Can we ignore Tcache and use the second one? Please clarify?
rahul sharma 5
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in
CO and Architecture
May 20, 2017
by
rahul sharma 5
907
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cache-memory
co-and-architecture
write-through
0
votes
0
answers
499
[COA] Memory Access
A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache,Cpu access it from cache.. If it is in main memory but not in the cache, 50 ns are needed to load it into the cache, and then the ... word on this system.Cache access time is 5 ns ,Main memory access time is 10 ns. Edit:- Disk accessed was mentioned twice.Updated it
rahul sharma 5
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in
CO and Architecture
May 20, 2017
by
rahul sharma 5
1.1k
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co-and-architecture
cache-memory
effective-memory-access
3
votes
1
answer
500
[CO] Memory Organization
3 level memory has the following specifications:- Level AccessTime/Word Block Size in words Hit Ratio 1 20 ns - .7 2 100 ns 2 .9 3 200 ns 4 1 If the referenced block is not in L1,then transfer from L2 to L1,If not in L2,then transfer from L3 to L2 to L1.How long will it take to access a block?
rahul sharma 5
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in
CO and Architecture
May 19, 2017
by
rahul sharma 5
2.1k
views
co-and-architecture
cache-memory
10
votes
3
answers
501
ISRO2017-21
A cache memory needs an access time of $30$ ns and main memory $150$ ns, what is average access time of CPU (assume hit ratio $= 80\%)?$ $60$ ns $30$ ns $150$ ns $70$ ns
sh!va
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in
CO and Architecture
May 7, 2017
by
sh!va
13.2k
views
isro2017
co-and-architecture
cache-memory
4
votes
2
answers
502
Patterson Hennessey
Which of the following cache designer guidelines are generally valid? 1. The shorter the memory latency, the smaller the cache block 2. The shorter the memory latency, the larger the cache block 3. The higher the memory bandwidth, the smaller the cache block 4. The higher the memory bandwidth, the larger the cache block
kauray
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CO and Architecture
May 1, 2017
by
kauray
1.5k
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cache-memory
co-and-architecture
reference-book
0
votes
1
answer
503
Testbook Test Series: CO & Architecture - Cache Memory
If a 16-way Set Associative cache is made up of 64 bit words , 16 words per line and 8192 sets, How big is the cache in Megabytes ?
Devwritt
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CO and Architecture
Apr 29, 2017
by
Devwritt
1.8k
views
co-and-architecture
testbook-test-series
cache-memory
0
votes
0
answers
504
Block replacement in cache
How we replace blocks in k-way set associative cache ? What strategy we follow?
elakashi sharma
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in
CO and Architecture
Apr 27, 2017
by
elakashi sharma
304
views
cache-memory
2
votes
1
answer
505
gate2000-12 cache memory
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is ... 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.
shal
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in
CO and Architecture
Apr 1, 2017
by
shal
462
views
cache-memory
2
votes
1
answer
506
False sharing in cache Line
Here is pseudo code for a multiprocessing purpose: set_num_threads(NUM_THREADS); double sum=0.0; sum_local[NUM_THREADS]; parallel region { int this_thread_id = get_thread_number(); // returns 0 to (no_of_threads-1) sum_local[this_thread_id] = 0.0; for (i ... I think frequent DRAM write back causing the problem, but not very clear, though. please explain a bit. @Arjun Sir
dd
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CO and Architecture
Mar 5, 2017
by
dd
1.1k
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co-and-architecture
cache-memory
non-gate
descriptive
3
votes
1
answer
507
Write back Cache with write allocate policy
Consider a computer with the following features: 90% of all memory accesses are found in the cache (hit ratio = 0.9); The block size is 2 words and the whole block is read on any miss; The CPU sends references to the cache at ... uses write allocate on a write miss. Calculate the percentage of the bus bandwidth used on the average if cache is WRITE BACK:
sh!va
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in
CO and Architecture
Mar 2, 2017
by
sh!va
1.7k
views
cache-memory
co-and-architecture
62
votes
10
answers
508
GATE CSE 2017 Set 1 | Question: 54
A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the $\textsf{TAG}$ field is $10$ bits. If the cache unit is now designed as a $16$-way set-associative cache, the length of the $\textsf{TAG}$ field is ____________ bits.
Arjun
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in
CO and Architecture
Feb 14, 2017
by
Arjun
19.5k
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gatecse-2017-set1
co-and-architecture
cache-memory
normal
numerical-answers
91
votes
9
answers
509
GATE CSE 2017 Set 1 | Question: 51
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory ... $10$ times. The number of conflict misses experienced by the cache is _________ .
Arjun
asked
in
CO and Architecture
Feb 14, 2017
by
Arjun
38.5k
views
gatecse-2017-set1
co-and-architecture
cache-memory
conflict-misses
normal
numerical-answers
29
votes
8
answers
510
GATE CSE 2017 Set 2 | Question: 53
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size $32$ bytes. Assume that a direct mapped cache having $512$ cache lines is used with this machine. The size of the tag field in bits is _______
Madhav
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CO and Architecture
Feb 14, 2017
by
Madhav
9.4k
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gatecse-2017-set2
co-and-architecture
cache-memory
numerical-answers
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