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Recent questions tagged cache-memory

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61

cache memory
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles. If cache miss rate is 2%, then the effective CPI for the system with the cache is ____.

someshawasthi asked in CO and Architecture Nov 17, 2022

by someshawasthi

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62

cache memory
Consider a process where each instruction takes on average 3 cycle and there are 1.8 references to memory per instruction. A program with 50000 instruction is executed on this machine using a split cache of 32KB, obtained a 85% bit rate, 3ns bit time and 21ns miss penalty the execution time for the cache is ___ (μsec)

someshawasthi asked in CO and Architecture Nov 16, 2022

by someshawasthi

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1 vote

1 answer

63

Zeal test series
A computer system uses $16-$bit memory addresses.It has a $16KB$ cache organized in a $4-$ way set associative manner with $64 $ bytes per cache block.Assume that size of each memory word is 2B .When a program is executed ,The processor read ... .All the above addresses shown in decimal values.Assume cache is initially empty .The number of addresses hit in the cache ?

Kabir5454 asked in CO and Architecture Nov 1, 2022

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1 answer

64

cache memory
THE size of memory required at cache controller to store the metadata is 2kbyte The metadata include tag bits 1 modified bit and 1 valid bit The cache contain 1KBlocks of 32 bytes each organized as directed mapped The size of Main memory is __ Mbytes?

Vaishnavi Gadhe asked in CO and Architecture Oct 25, 2022

by Vaishnavi Gadhe

503 views

2 votes

0 answers

65

Operating System: Self Doubt - Memory Management
Considering a system with Single-Level page table, with a TLB to reduce the access time of pages. A cache is also provided with the main memory. All the pages ultimately reside in MM. (assuming there's no page fault). Let, TLB Hit Ratio = x TLB Access ... for TLB miss it will be (a+c+p). But if this is true, why can't we store Page Table in a Cache?

DebRC asked in Operating System Sep 14, 2022

by DebRC

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1 answer

66

SKMAKM asked in CO and Architecture Sep 2, 2022

by SKMAKM

336 views

1 vote

1 answer

67

Gate Zeal@ Test Series 2022
Ans is 2168 Please help someone

SKMAKM asked in CO and Architecture Sep 2, 2022

by SKMAKM

256 views

5 votes

1 answer

68

GO Classes Test Series 2023 | CO and Architecture | Test 3 | Question: 2
If a memory system consists of a single external cache with an access time of $20$ ns and a hit rate of $0.92,$ and a main memory with an access time of $60$ ns, what is the effective memory access time, in ns, of this system?

GO Classes asked in CO and Architecture Aug 31, 2022

361 views

1 vote

1 answer

69

ISI 2021 | PCB CS | Question: 7.b
Consider a $4$-way set associative cache mapping, in which the cache blocks are grouped into sets and each set has $4$ blocks. There are $16$ cache blocks in total. The following memory block requests arrive in order when ... . Show the cache configuration (along with intermediate configurations) on meeting the above memory requirements. What is the hit ratio?

admin asked in CO and Architecture Aug 24, 2022

by admin

737 views

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70

Zeal Test
Question : Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 mapped??

lalitver10 asked in CO and Architecture Aug 19, 2022

702 views

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Recent questions tagged cache-memory