Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
Recent questions tagged data-path
1
vote
1
answer
1
NIELIT 2016 DEC Scientist B (IT) - Section B: 47
The ________ is the physical path over which a message travels. Path Protocol Route Medium
admin
asked
in
Computer Networks
Mar 31, 2020
by
admin
937
views
nielit2016dec-scientistb-it
computer-networks
data-path
15
votes
4
answers
2
GATE CSE 2020 | Question: 4
Consider the following data path diagram. Consider an instruction: $R0 \leftarrow R1 +R2$. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts $r$ and $w$ ... of the above steps? $2,1,4,5,3$ $1,2,4,3,5$ $3,5,2,1,4$ $3,5,1,2,4$
Arjun
asked
in
CO and Architecture
Feb 12, 2020
by
Arjun
8.5k
views
gatecse-2020
co-and-architecture
data-path
1-mark
0
votes
0
answers
3
Doubt on Data Path
In Single bus Architecture for a simple add operation ,we know there are 8 cycles required, where 1st three for Fetch cycle and Others are for execution cycle Steps Action 1. $PC_{out},MAR_{in},Read, Clear-Y,Set Carry Into ALU,Add,Z_{in}$ 2. ... T? 3) Question is only asking clock cycles for execution cycle. Then why we are considering Fetch and Execution cycles in our answer?
srestha
asked
in
CO and Architecture
Sep 13, 2018
by
srestha
527
views
co-and-architecture
data-path
doubt
0
votes
1
answer
4
virtual gate
Manoja Rajalakshmi A
asked
in
CO and Architecture
Nov 9, 2017
by
Manoja Rajalakshmi A
331
views
data-path
1
vote
0
answers
5
GATE CSE 1988 | Question: 4i
An $8$-bit data path is to be set up using two $4$-bit ALU's and suitable multiplexers. The ALU's accept two operands $A$ and $B$ on which a total of $16$ operations can be performed. The operand $A$ is from one of two ... a bus. List the data path control signals, and estimate the minimum width of a signal microcode word needed for the generation of these signals.
go_editor
asked
in
CO and Architecture
Dec 19, 2016
by
go_editor
530
views
gate1988
descriptive
co-and-architecture
data-path
unsolved
10
votes
1
answer
6
GATE CSE 1990 | Question: 8a
A single bus CPU consists of four general purpose register, namely, $R0, \ldots, R3, \text{ALU}, \text{MAR}, \text{MDR}, \text{PC}, \text{SP}$ and $\text{IR}$ (Instruction Register). Assuming suitable microinstructions, write a microroutine for the instruction, $\text{ADD }R0, R1$.
makhdoom ghaya
asked
in
CO and Architecture
Nov 24, 2016
by
makhdoom ghaya
2.0k
views
gate1990
descriptive
co-and-architecture
data-path
55
votes
12
answers
7
GATE CSE 2005 | Question: 80
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in ... $2$ $3$ $4$ $5$
go_editor
asked
in
CO and Architecture
Apr 24, 2016
by
go_editor
24.1k
views
co-and-architecture
normal
gatecse-2005
data-path
machine-instruction
99
votes
12
answers
8
GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement ... $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.
Akash Kanase
asked
in
CO and Architecture
Feb 12, 2016
by
Akash Kanase
22.6k
views
gatecse-2016-set2
co-and-architecture
data-path
normal
numerical-answers
4
votes
1
answer
9
The ALU, the bus and all the register are identical in size. the instruction "memory write"
The ALU, the bus and all the register are identical in size. The instruction "memory write" has the register transfer interpretation M[(R1)] ← R2. The minimum number of clock cycles needed for execution cycle of this instruction if memory write completion takes 1 cycle is a) 2 b)3 c)4 d)5
yes
asked
in
CO and Architecture
Nov 20, 2015
by
yes
875
views
co-and-architecture
data-path
47
votes
6
answers
10
GATE CSE 2005 | Question: 79
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the ... $2$ $3$ $4$ $5$
Kathleen
asked
in
CO and Architecture
Sep 22, 2014
by
Kathleen
24.3k
views
gatecse-2005
co-and-architecture
machine-instruction
data-path
normal
54
votes
11
answers
11
GATE CSE 2001 | Question: 2.13
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$ wide. $\textsf{SP}$ and $\textsf{MAR}$ are $16$-$bit$ registers. The ... $\textsf{CPU}$ clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$
Kathleen
asked
in
CO and Architecture
Sep 14, 2014
by
Kathleen
21.0k
views
gatecse-2001
co-and-architecture
data-path
machine-instruction
normal
To see more, click for the
full list of questions
or
popular tags
.
Subscribe to GATE CSE 2024 Test Series
Subscribe to GO Classes for GATE CSE 2024
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Post GATE 2024 Guidance [Counseling tips and resources]
GATE CSE 2024 Result Responses
[Project Contest] Pytorch backend support for MLCommons Cpp Inference implementation
Participating in MLCommons Inference v4.0 submission (deadline is February 23 12pm IST)
IIITH PGEE 2024 Test Series by GO Classes
Subjects
All categories
General Aptitude
(3.5k)
Engineering Mathematics
(10.4k)
Digital Logic
(3.6k)
Programming and DS
(6.2k)
Algorithms
(4.8k)
Theory of Computation
(6.9k)
Compiler Design
(2.5k)
Operating System
(5.2k)
Databases
(4.8k)
CO and Architecture
(4.0k)
Computer Networks
(4.9k)
Artificial Intelligence
(79)
Machine Learning
(48)
Data Mining and Warehousing
(25)
Non GATE
(1.4k)
Others
(2.7k)
Admissions
(684)
Exam Queries
(1.6k)
Tier 1 Placement Questions
(17)
Job Queries
(80)
Projects
(11)
Unknown Category
(870)
64.3k
questions
77.9k
answers
244k
comments
80.0k
users
Recent questions tagged data-path
Recent Blog Comments
category ?
Hi @Arjun sir, I have obtained a score of 591 in ...
download here
Can you please tell about IIT-H mtech CSE self...
Please add your admission queries here:...