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Counting number of "AND" and "OR" gates in a multiplexer and decoder. How do we approach such questions?

tishhaagrawal asked in Digital Logic Dec 4, 2023

by tishhaagrawal

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Madeeasy ots Digital Logic Combinational Circuits
I am confused in active low enable input and active low output?

Sajal Mallick asked in Digital Logic Nov 23, 2023

by Sajal Mallick

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ISI2020-PCB-CS: 10
Suppose instead of a decoder with $n$ input bits ( $n$ is even) to access a memory of size $2^{n}$, one uses two decoders of input sizes $k$ bits and $(n-k)$ bits. Explain how these two decoders can be used to access the ... address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.

admin asked in Digital Logic Aug 8, 2022

by admin

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ISI2021-PCB-C10
Suppose instead of a decoder with n input bits (n is even) to access a memory of size 2^n, one uses two decoders of input sizes k bits and (n-k) bits. Explain how these two decoders can be used to access the memory of size 2^N. ... address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.

jatin29 asked in Digital Logic May 3, 2022

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Made Easy Test Series
A 3 to 8 decoder is shown below: All output lines of decoder will be high when all the input I1, I2, I3 are; are high and G1 , G2 are low are high and G1 is high , G2 is low are high and G1 is low , G2 is high are high and G1 , G2 are high Please someone help to understand the logic behind this question. Why we have to disable the Decoder to make all the outputs high ?

Rajat Agrawal007 asked in Digital Logic Nov 22, 2021

by Rajat Agrawal007

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3 to 8 line Decoder (Combinational Circuit)
If F1 = ∑m(1,2,4,7) and F2 = ∑m(3,5,6,7), implement them using 3 to 8 line decoder. Comment on their logic operations.

gikovi asked in Digital Logic Sep 25, 2021

by gikovi

597 views

17 votes

4 answers

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GATE CSE 2020 | Question: 20
If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .

Arjun asked in Digital Logic Feb 12, 2020

by Arjun

9.6k views

3 votes

2 answers

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Made Easy Test Series: Digital Logic
A $3\times 8$ decoder with $2$ enable inputs is used to address $8$ block of memory. What will be the size of each memory block when addressed from a $16$ bit bus with $2$ MSB’s used to enable the decoder?

srestha asked in Digital Logic May 15, 2019

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Morris Mano Edition 3 Exercise 5 Question 18 (Page No. 199)
Construct a $5 \times 32 $ decoder with four $3\times8$ decoders with enable and one $ 2 \times 4$ decoder. use a block diagram also.

ajaysoni1924 asked in Digital Logic Apr 3, 2019

by ajaysoni1924

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Morris Mano Edition 3 Exercise 5 Question 17 (Page No. 199)
Draw the logic diagram of a 2-to-4 line decoder with only NOR gates. Include an Enable input.

ajaysoni1924 asked in Digital Logic Apr 3, 2019

by ajaysoni1924

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11

DRDO 2009
The number of 2-to-4 line decoders with enable input needed to construct a 4-to-16 line decoder are?

Sambhrant Maurya asked in Digital Logic Jan 3, 2019

by Sambhrant Maurya

1.8k views

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Made easy theory book
Solve this.

Jyoti Kumari97 asked in Digital Logic Dec 30, 2018

by Jyoti Kumari97

842 views

1 vote

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MadeEasy Test Series: Digital Logic - Decoder
A $3 \times 8$ decoder with two enables inputs is to be used to address 8 blocks of memory. What will be the size of each memory block when addressed from a sixteen-bit bus with two MSBs used to enable the decoder? $i)2k$ $ii)4k$ $iii)16k$ $iv) 64k$ What does “two enable inputs is to be used” mean? I am not able to visualize the circuit.

shreyansh jain asked in Digital Logic Dec 28, 2018

by shreyansh jain

2.2k views

1 vote

3 answers

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NIELIT 2018-39
A RAM chip has a capacity of $1024$ words of $8$ bits each $(1K \times 8)$. The number of $2 \times 4$ decoders with enable line needed to construct a $32 K \times 8$ RAM from $1K \times 8$ RAM is $4$ $5$ $6$ $7$

Arjun asked in Digital Logic Dec 7, 2018

by Arjun

2.7k views

1 vote

2 answers

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Na462 asked in CO and Architecture Nov 7, 2018

by Na462

1.0k views

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Recent questions tagged decoder