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Recent questions tagged operand-forwarding
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1
Operand Forwarding [ Self Doubt }
I have a Self doubt question on Operand Forwarding . The data forwarded should be done in EX-EX stage or Mem-EX ? Which one to follow and when ? Using EX-EX we require less no. of cycles.
Deepak9000
asked
in
CO and Architecture
Nov 5, 2023
by
Deepak9000
241
views
pipelining
co-and-architecture
operand-forwarding
data-dependency
0
votes
1
answer
2
Operand forwarding Made Easy Question
Consider 4-stage (IF, ID, EX, WB) pipeline used to execute the following code. All instructions are spending are spending one cycle on all the stages but ALU instructions are spending 3 cycles on 3rd stage. I1: LOAD R0, ... Number of cycles are saved using operand forwarding over without operand forwarding is? Can someone please explain by drawing the diagram?
Chaitanya Kale
asked
in
CO and Architecture
Jan 30, 2023
by
Chaitanya Kale
913
views
pipelining
co-and-architecture
operand-forwarding
made-easy-test-series
2
votes
0
answers
3
Split Phase | Self-Doubt | COA
How is split phase implemented in the hardware? For common register access between two stages, how is one clock cycle (Giving half a clock cycle to each of the stages) enough to satisfy work for both stages? Any reference to standard resources will also help.
DebRC
asked
in
CO and Architecture
Dec 6, 2022
by
DebRC
430
views
co-and-architecture
operand-forwarding
operating-system
self-doubt
split-phase
0
votes
1
answer
4
COA Applied Course
Assume that we are using the classic MIPS five-stage(IF, ID, EX, MEM and WB) integer pipeling.
Sagar475
asked
in
CO and Architecture
Dec 26, 2021
by
Sagar475
415
views
co-and-architecture
pipelining
operand-forwarding
1
vote
1
answer
5
GATE appliedroots test series
I have 3 doubts in the following solution: Doubt 1: In red colour While I1 is in the Memory-access stage, how can I4 fetch the instruction from the memory? Isn't this a structural dependency problem? Doubt 2: In blue ... operate with register only so the memory-access stage shouldn't happen for these instructions, correct? Solution as per my understanding:
Ashutosh_Mishra
asked
in
CO and Architecture
Dec 12, 2021
by
Ashutosh_Mishra
479
views
co-and-architecture
pipelining
operand-forwarding
0
votes
0
answers
6
NPTEL Assignment Question
Consider the following code : Load R1,M Load R2,N CMP R1,R2 JGE END Store [300],R2 END: Store [300],R1 Assume that M=30 and N=25. The above sequence of instructions is to be executed on a pipelined processor with IF , ... instructions. The branch outcome is known after EX stage. Determine the number of clock cycles required for completion of execution of all instructions.
rsansiya111
asked
in
CO and Architecture
Dec 8, 2021
by
rsansiya111
363
views
co-and-architecture
pipelining
operand-forwarding
nptel-quiz
branch-conditional-instructions
2
votes
2
answers
7
Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .
DIYA BASU
asked
in
CO and Architecture
Feb 18, 2019
by
DIYA BASU
598
views
co-and-architecture
pipelining
operand-forwarding
0
votes
1
answer
8
CAO ME
Consider a pipeline processor with 5 stages, Instruction Fetch (IF). Instruction Decode and Operand Fetch (ID), Operation performed (OP). Data memory access (MA) and Write back (WB). The IF, ID, MA and WB stages takes 1 clock cycle each ... for MUL instruction. The minimum number of clock cycles are needed to complete following sequence of instruction if operand forwarding is used ________.
balchandar reddy san
asked
in
CO and Architecture
Jan 20, 2019
by
balchandar reddy san
497
views
co-and-architecture
pipelining
operand-forwarding
0
votes
0
answers
9
Test series
#Pipelining Please clear my doubt. In a 5 stage pipelining (IF, ID, EX, MA, WB) there are 5 instruction given. Instruction 1 : R2 ← R0 + R1; Instruction 2 : R1 ← R2 - R1; Instruction 3 : R0 ← R2 - R0; Instruction 4 : R2 ← ... My understanding is whenever dependency is there b/w instruction, ID phase of Next instruction will occur after EX phase of previous Instruction. It is correct ?
aditya dhanraj
asked
in
CO and Architecture
Jan 13, 2019
by
aditya dhanraj
169
views
co-and-architecture
pipelining
operand-forwarding
0
votes
0
answers
10
Madeeasy COA Ques
Please explain.
Shubham Kumar Gupta
asked
in
CO and Architecture
Jan 9, 2019
by
Shubham Kumar Gupta
371
views
co-and-architecture
pipelining
operand-forwarding
0
votes
2
answers
11
Data forwarding in pipelining
Data forwarding is used to avoid which type of conflict?? (1) RAW (2) WAR (3) WAW (4) RAR
Abhilash Mishra
asked
in
CO and Architecture
Jan 2, 2019
by
Abhilash Mishra
1.2k
views
pipelining
co-and-architecture
operand-forwarding
data-dependency
0
votes
2
answers
12
MadeEasy Test Series: CO & Architecture - Pipelining
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)
Markzuck
asked
in
CO and Architecture
Dec 25, 2018
by
Markzuck
946
views
co-and-architecture
pipelining
made-easy-test-series
operand-forwarding
0
votes
0
answers
13
CO pipelining
consider a 4-stage pipeline (IF, ID, EX, WB) used to execute the following code. All the instructions are spending 1 cycle in all the stags but MUL takes 4 cycles. Div takes 3 cycles in EX stages. The pipeline uses operand forwarding as an optimization a- how many cycles are required to complete ... ? I1 : MUL r0 , r1 , r2 I2 : DIV r3 , r1 , r2 I3: SUB r4, r3, r2 I4: ADD r5, r4, r1
hitendra singh
asked
in
CO and Architecture
Dec 24, 2018
by
hitendra singh
940
views
co-and-architecture
pipelining
operand-forwarding
2
votes
0
answers
14
bypassingw
what is difference between operand forwarding and bypassing?
Lone Wolf
asked
in
CO and Architecture
Dec 21, 2018
by
Lone Wolf
809
views
co-and-architecture
operand-forwarding
1
vote
0
answers
15
https://gateoverflow.in/753/gate2001-12?show=279851#c279851
doubt in this gate question- https://gateoverflow.in/753/gate2001-12?show=279851#c279851 In instruction I3 how is it getting the value of r2 which is computed in I1 instruction?? Can memory access stage read the value of updated register values of write back stage?? please resolve my doubt.
sushmita
asked
in
CO and Architecture
Dec 18, 2018
by
sushmita
419
views
co-and-architecture
pipelining
operand-forwarding
0
votes
1
answer
16
general doubt on pipelining
we do forwarding from WB stage to EX or from WB to MEM stage??
sushmita
asked
in
CO and Architecture
Dec 17, 2018
by
sushmita
399
views
co-and-architecture
pipelining
operand-forwarding
0
votes
0
answers
17
#madeeasy test series
Soumya Tiwari
asked
in
CO and Architecture
Dec 12, 2018
by
Soumya Tiwari
152
views
co-and-architecture
pipelining
operand-forwarding
0
votes
0
answers
18
SELF DOUBT
PLEASE explain what is operand forwarding and how we are going to implement this in stages during execution of the instruction ??? and also when to use it in according to question property and not when to use it ? pls check these questions of same concept also ... this phenomena . i am not getting it if someone got the link of operand forwarding from where should i hv done this plzz add
Deepanshu
asked
in
CO and Architecture
Nov 3, 2018
by
Deepanshu
273
views
co-and-architecture
pipelining
operand-forwarding
self-doubt
0
votes
0
answers
19
Doubt clearing
Incase of operand forwarding in RISC pipeline with stages Instruction fetch (IF) Instruction decode (ID) Execute (EX) Memory Access (MA) Write Back (WB) If it is not mentioned from which stage to which stage the operand is forwarded, should I by default take that it is forwarded from MA stage to ID stage?
nepobose
asked
in
CO and Architecture
Oct 31, 2018
by
nepobose
181
views
co-and-architecture
pipelining
operand-forwarding
doubt
0
votes
1
answer
20
Test_CO1_Q35
Assume branch instruction occurs 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forwarding, the load delay slot is one cycle and can be filled 60% if the time with useful instructions, 20% of the ... What is the new CPI due to load delay slots and branch hazards? A. 1.204 B. 1.404 C. 2.204 D. 4.404
BOB
asked
in
CO and Architecture
Oct 15, 2018
by
BOB
254
views
co-and-architecture
pipelining
operand-forwarding
branch-conditional-instructions
test-series
1
vote
1
answer
21
MadeEasy Test Series: CO & Architecture - Pipelining
The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction output present at 4th stage and ALU instruction output is at third stage. Assume each stage ... must be inserted to achieve CPI = 1 by using Operand Forwarding ? A. 3 B. 4 C. 5 D. 6
Na462
asked
in
CO and Architecture
Oct 13, 2018
by
Na462
946
views
co-and-architecture
pipelining
operand-forwarding
made-easy-test-series
0
votes
0
answers
22
ME test series
newdreamz a1-z0
asked
in
CO and Architecture
Oct 7, 2018
by
newdreamz a1-z0
339
views
co-and-architecture
machine-instruction
operand-forwarding
clock-cycles
numerical-answers
made-easy-test-series
0
votes
0
answers
23
self doubt
OPERAND FORWARDING work only when following cases 1) only when ALU(+,-,*,/) operation present 2) In only RAW Hazard . Am i right?
VIDYADHAR SHELKE 1
asked
in
CO and Architecture
Sep 25, 2018
by
VIDYADHAR SHELKE 1
221
views
co-and-architecture
operand-forwarding
self-doubt
0
votes
0
answers
24
Operand Forwarding Doubt
I dont understand here:- Load R2,(R3) 1. Fetch 2. Decode: Rz <--- Address of R3 given in instruction 3. Compute : NOP 4. Memory Memory address <---[RZ] , read memory, Ry <---MemData 5. R2 <--- [Ry] If i wrote above right then R2 is available at Cycle 5 but there is extra stall at cycle 6 for Instruction j+1 why ??
Na462
asked
in
CO and Architecture
Sep 3, 2018
by
Na462
1.1k
views
pipelining
co-and-architecture
operand-forwarding
3
votes
0
answers
25
#Data Hazards #Operand Forwarding #CO
Is there any difference in calculating data hazards and dependencies? Doubt 1:I've read that in data dependencies calculation we chose adjacent instructions only? IS THIS TRUE. Doubt 2:Calculation of RAW,WAR,WAW hazards include ... adjacent.IS THIS TRUE There are many sources which are confusing Please Explain how to calculate dependencies and hazards.
rasto mapp
asked
in
CO and Architecture
Jan 13, 2018
by
rasto mapp
583
views
co-and-architecture
pipelining
data-hazards
hazards
operand-forwarding
1
vote
1
answer
26
Doubt in Pipelining Terminology
In pipelining questions we have "If operand forwarding is there " and "If operand forwarding is not there " Please explain this difference and how to draw the chart for both the cases .
Parshu gate
asked
in
CO and Architecture
Dec 10, 2017
by
Parshu gate
373
views
pipelining
co-and-architecture
operand-forwarding
1
vote
1
answer
27
Pipeline
Give answer for question no. 12 please! provide detailed answer.
learner_geek
asked
in
CO and Architecture
Oct 15, 2017
by
learner_geek
448
views
co-and-architecture
pipelining
operand-forwarding
data-hazards
2
votes
1
answer
28
Dealing with ALU-ALU forwarding
Consider two instruction sequences: a. SW R16,-100(R6) LW R4, 8(R16) ADD R5,R4,R4 b. OR R1,R2,R3 OR R2,R1,R3 OR R1,R1,R2 Add NOP instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage).
GateAspirant999
asked
in
CO and Architecture
Jun 26, 2017
by
GateAspirant999
2.4k
views
co-and-architecture
pipelining
operand-forwarding
1
vote
1
answer
29
Pipeline
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output present in 4th stage ALU instruction output ... What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.
srestha
asked
in
CO and Architecture
Feb 4, 2017
by
srestha
1.6k
views
co-and-architecture
pipelining
operand-forwarding
0
votes
2
answers
30
Pipeline (With split phase- With forwarding)
A $5-$ stage pipelined processor has IF,ID,EX,MEM and WB . WB stage operation is divided into two parts. In the first part register write operation and in second part register read operation is performed. The latency of those stages are $300,400,500,500,300$ ... SUB $R_{1},R_{7},R_{4}$ $R_{1} <- R_{7} - R_{4}$ The program execution time__________ns?
monty
asked
in
CO and Architecture
Jan 29, 2017
by
monty
1.4k
views
co-and-architecture
operand-forwarding
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