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Recent questions tagged paging

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1

Paging
If Page size = Frame size is always true and offset in Logical address = offset in physical address holds Then how/why Logical address size can come different than physical address size?

Mrityudoot asked in Operating System Mar 20

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0 answers

2

memory management
we have 8 pages (each side 32B) to store in physical memory of 2^32 bits how many bits are required to identify each page , according to me 3 bits are required but that is wrong plz explain why

SSR17 asked in Operating System Feb 8

by SSR17

186 views

9 votes

2 answers

3

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 36
Assume a linear page table, with a 1-byte page-table entry. Assume physical and virtual address spaces of size 128 bytes with 32-byte pages. The page-table base register is set to physical address 16. The contents of ... What are the physical addresses that will get referred in fetch and execute of the above instruction? 10 42 102 70

GO Classes asked in Operating System Feb 5

561 views

5 votes

1 answer

4

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 21
Consider a virtual memory system that uses paging. Virtual and physical addresses are both $32$ bits long, and the page size is $4 \textsf{KB}=2^{12}$ bytes. A process $\text{P}_1$ has the following page table. ... $\textsf{0x00003b65}$ $\textsf{0x00875b65}$ $\textsf{0x00875}$ Translation is not possible as per the given page table

GO Classes asked in Operating System Jan 28

357 views

6 votes

2 answers

5

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 45
Imagine a computer with a $32$-bit virtual address space and $\text{1 KB}$ pages. It uses a two-level page table system, with page-sized chunks at the inner level(not at the outer level). Suppose the code is located at address $0,$ and there are ... is $4$ Bytes.) $64 \mathrm{~KB}$ $2 \mathrm{~KB}$ $66 \mathrm{~KB}$ $16 \mathrm{MB}$

GO Classes asked in Operating System Jan 28

708 views

4 votes

1 answer

6

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 9
Consider a system with $4 \mathrm{~GB}$ of physical memory and $64 \mathrm{~GB}$ of Virtual Memory. The page size is $4 \mathrm{~KB}$. Recall that the page table is stored in physical memory and consists of PTEs (page ... each page could store $2048$ PTEs. How many pages does our page table occupy if we have a single-level page table?

GO Classes asked in Operating System Jan 21

607 views

9 votes

1 answer

7

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 20
Suppose that pages are $512 \mathrm{~B}$ and each page table entry is $4$ bytes. Assume that somehow the virtual and physical address spaces were both $4$ ... PTE we would look at? $\textsf{0x10000000}$ $\textsf{0x10000001}$ $\textsf{0x10000004}$ $\textsf{0x10000345}$

GO Classes asked in Operating System Jan 13

610 views

0 votes

0 answers

8

Made Easy Question : Multilevel Paging system, please refer the question below.
In this question, they have asked for memory requirements for page tables across the levels, solving which I am getting number of level 3 page tables as 2^8. Below is a brief of my approach, can anybody please explain if I am right or ... 3 PTs + level 4 PTs = 1 + 1 + 2^8 + 2^16 Where am I doing wrong? Please explain.

tishhaagrawal asked in CO and Architecture Dec 5, 2023

by tishhaagrawal

233 views

0 votes

1 answer

9

OPERATING SYSTEM
Assuming 3-level of paging is used by a paging system and a TLB for address translation. Calculate Average memory access time if each main memory access takes 100ns and TLB access time is 10ns, page fault service time is given as 200ns and TLB hit ratio is 80% and page fault rate is 10%.

24aaaa23 asked in Operating System Oct 2, 2023

328 views

0 votes

1 answer

10

Ace Test Series | Operating System | Paging
A machine supports a 48 bit virtual address and 32 bit physical address. Pages are 8KB. If the page table entry contains besides other information, one V/I bit, 1R, 1M and 2 bits for page protection. What is the page table size in bytes? 86 MB 128 MB 96 MB 512 MB

none30 asked in Operating System Sep 4, 2023

by none30

297 views

0 votes

1 answer

11

Can anyone explain , in the concept of segmentation . let the base address of a particular segment is 1900 and the limit of the segment is 400(i.e., size limit). Exactly what does it represent at the address 1900. Is it a page or group of pages or words

Unique_999 asked in Operating System Sep 3, 2023

265 views

0 votes

2 answers

12

Memory Management And Paging
Can Any explain the relationship between The “ Word Size “ and “ Logical Address Space “

Unique_999 asked in Operating System Aug 17, 2023

296 views

0 votes

1 answer

13

Paging , performance of paging w.r.t to space
Consider a System using Paging technique with an Address Space of65,536 Bytes. The Page Size in this System is 4096 Bytes. The Program Consists of Text, Data and Stack Sections as per the specifications given below: Text: 32,768 Bytes Data ... Address Space? b)What is the Maximum Page Size in Bytes such that the Program Fits in the Given Address Space?

sumantsingh_ asked in Operating System Jun 4, 2023

by sumantsingh_

277 views

0 votes

1 answer

14

Andrew S. Tanenbaum (OS) Edition 4
A computer provides each process with 65536 bytes of address space divided into pages. A particular program has a text size of 32768 bytes, a data size of 16386 bytes, and a stack size of 15870 bytes. What is the maximum page size in bytes such ... the given address space? Each page must contain either text, data, or stack, not a mixture of two or three of them.

Syntax-error asked in Operating System Apr 24, 2023

by Syntax-error

408 views

2 votes

2 answers

15

TLB with fault rate.
consider a paging system uses 1 level page table residing in RAM and TLB. RAM access time is 55 ns while TLB lookup takes 17 ns. Each page transfer takes upto 4700 ns to/from swap space. Miss ratio of TLB is 95% and Page fault ratio is 33%. Calculate the EMAT when TLB update time is negligible.

shubhamsingh872 asked in Operating System Apr 18, 2023

by shubhamsingh872

620 views

0 votes

1 answer

16

#Memory Management #Paging #GATE
Consider a system which has LAS = PAS = ‘s’ bytes, page size is p bytes,Page table entry size is ‘e’ bytes Memory is byte addressable. Then what is the optimal value of page size by minimizing the memory overhead of maintaining the page table and internal fragmentation in paging?

Samridh28 asked in Operating System Apr 3, 2023

447 views

1 vote

1 answer

17

GO Classes 2023 | IIITH Mock Test 1 | Question: 29
Consider a system with $\mathrm{N}$ bytes of physical RAM, and $\mathrm{M}$ bytes of virtual address space per process. Pages and frames are $\text{K}$ bytes in size. Every page table entry is $\mathrm{P}$ bytes in size, accounting for the extra flags ... $\mathrm{M} / \mathrm{K} \ast \mathrm{P}$ $\mathrm{N} / \mathrm{P} \ast \mathrm{~K}$

GO Classes asked in Operating System Mar 26, 2023

644 views

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Recent questions tagged paging