Dark Mode

Recent questions tagged speedup

0 votes

0 answers

1

UGC NET CSE | June 2008 | Part 2 | Question: 46
Amdahl's law states that the maximum speedup $\text{S}$ achievable by a parallel computer with ' $\mathrm{p}$ ' processors is given by : $\mathrm{S} \leq \mathrm{f}+(1-\mathrm{f}) / \mathrm{p}$ ... $\mathrm{S} \leq 1 /[1-\mathrm{f}+\mathrm{f} / \mathrm{p}]$

admin asked in CO and Architecture Jan 6

by admin

68 views

0 votes

1 answer

2

Unacadmey book
If we have a non pipeline processor which has a cycle time of 40 ns and average CPI of 5.4 .Assuming a 5 stage pipeline model calculate the speed up of pipeline over non pipeline processor.

Praful jha asked in CO and Architecture Jul 8, 2023

441 views

0 votes

1 answer

3

Question on Pipelining
In a pipeline the maximum ideal speed-up is 5. Let the percentage of unconditional branches in a set of typical program be 5% and that of conditional branches be 10%. If 70% of the conditional branches are taken, calculate % loss of speed-up due to branch instructions. It is very difficult to understand this question and solve it. Please help.

Swarnava Bose asked in CO and Architecture Jul 2, 2022

by Swarnava Bose

1.1k views

0 votes

1 answer

4

Program runs in 100s . Multiplies 80 % of program . Designer M can improve speedup of multiply operations . Now , I am a user and I need to make MY program 5 times faster . How much speedup of multiply instructions should M achieve to allow me to reach my overall speedup goal ?

Sara86568 asked in CO and Architecture Jun 21, 2022

964 views

0 votes

2 answers

5

speedup in pipelining made easy & nptel
Which approach is correct? ASSIGNMENT LINK :-- https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdf nptel assignment q-1 Caption

farmanahmed888 asked in CO and Architecture Jan 6, 2022

by farmanahmed888

537 views

0 votes

1 answer

6

ISRO | ISRO CS 2020 | Question 6
Consider a 5-segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (If an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline.). (A) 5 (B) 4.03 (C) 4.81 (D) 4.17

ProtonicRED asked in CO and Architecture Dec 14, 2021

572 views

4 votes

3 answers

7

NIELIT 2016 DEC Scientist B (CS) - Section B: 23
A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration of the pipeline for $100$ tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$

admin asked in CO and Architecture Mar 31, 2020

by admin

2.2k views

2 votes

1 answer

8

UGC NET CSE | June 2019 | Part 2 | Question: 20
Suppose that a computer program takes $100$ seconds of execution time on a computer with multiplication operation responsible for $80$ seconds of this time. How much do you have to improve the speed of the multiplication operation if you are ... this program four times faster? $14$ times faster $15$ times faster $16$ times faster $17$ times faster

Arjun asked in CO and Architecture Jul 2, 2019

by Arjun

5.9k views

1 vote

1 answer

9

MadeEasy Full Length Test 2019: CO & Architecture - Speedup

jatin khachane 1 asked in CO and Architecture Jan 23, 2019

by jatin khachane 1

464 views

0 votes

1 answer

10

Made Easy
A hypothetical 5 stage processor is designed in which branch is predicted at 3 stage and each stage takes 1 cycle to compute its task. If f is the probability of an instruction being a branch instruction then what is the value of F such that speed up is atleast 3?

anjali007 asked in CO and Architecture Jan 23, 2019

430 views

0 votes

2 answers

11

Pipeline Efficiency
A pipeline has a speedup factor of 5 and operating at 70% efficiency. How many stages are there in the pipeline?

jatin khachane 1 asked in CO and Architecture Jan 22, 2019

by jatin khachane 1

2.1k views

0 votes

0 answers

12

bts1jimin asked in CO and Architecture Jan 21, 2019

300 views

0 votes

0 answers

13

ME mock 1
In an enhanced CPU, the speed of a floating point operations has been increased by 30% and the speed of a fixed point operations has been increased by 20%. In the original design floating point operations used to take twice the time compared to fixed point ... number of floating point instructions to the number of fixed point instructions is 2 : 3 is ________. (Upto 2 decimal places)

balchandar reddy san asked in CO and Architecture Jan 19, 2019

by balchandar reddy san

285 views

1 vote

0 answers

14

Speedup in coa
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.

Nandkishor3939 asked in CO and Architecture Jan 19, 2019

by Nandkishor3939

774 views

0 votes

0 answers

15

MadeEasy Test Series: CO & Architecture - Speedup
A hypothetical processor on cache read miss require one clock to send an address to MM and eight clock cycle to access a 64 bit word from MM to processor cache.miss rate of read is decreased from 14.8% to 2.6% when line size of cache is ... bz , the complete line got transfer when request of one word is made in ans key it is 4*(1+8) mentioned

Learner_jai asked in CO and Architecture Jan 17, 2019

359 views

0 votes

1 answer

16

ME TEST SERIES QUESTION ON PIPELINE

Shankar Kakde asked in CO and Architecture Jan 16, 2019

by Shankar Kakde

429 views

0 votes

2 answers

17

made easy
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its tasks. If f is the probability of an instruction being branch instruction then the value of f such that speedup is atleast 3 is____

Harshit Bajpai asked in CO and Architecture Jan 14, 2019

by Harshit Bajpai

1.0k views

1 vote

3 answers

18

MadeEasy Subject Test: CO & Architecture - Cache Memory
A cache memory is 30 times faster than main memory (MM) and 50% of the time cache is referred for the execution of instruction. The performance is gained by introducing this cache is ________. What I did EMAT = 0.5(M/30)+0.5(M/30+M) = 32M/60 speed up= (M)/32M/60) =60/32=1.875 answer given is 1.90-1.97 (using amdhal’s law)

Shivam Kasat asked in CO and Architecture Jan 13, 2019

by Shivam Kasat

876 views

0 votes

0 answers

19

madeeasy
Consider a 5 stage pipeline with IF , ID, EX, WB and MA having latencies (in ms) 3,8,5,6,4. What is average CPI of non pipeline CPU when speed up achieved by to pipeline is 4? I think answer is wrong For non pipe line total time = Total number of ... * time for each cycle calculation For pipeline version total time = Total number of instruction * max(3,8,5,6,4) So No role of CPI

mehul vaidya asked in CO and Architecture Jan 12, 2019

by mehul vaidya

309 views

2 votes

1 answer

20

MadeEasy Test Series: CO & Architecture - Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to ... up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)

Jay Bhutada 1 asked in CO and Architecture Jan 9, 2019

by Jay Bhutada 1

676 views

0 votes

0 answers

21

garimanand asked in CO and Architecture Jan 6, 2019

165 views

Page:

1
2
3
next »

Recent questions tagged speedup