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Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ $$\begin{array}{|l|l|c|} \hline \text {Instruction}  &  \text{Operation }& \text{Instruction size} \\&& \text{(in words)} \\\hline \text{MOV $R_1,5000$} & \text{$R_1$} \leftarrow  \text{Memory$[5000]$}& \text{$2$} \\\hline\text{MOV $R2,(R1)$} & \text{$R2$} \leftarrow  \text{Memory$[(R_1)]$}& \text{$1$} \\\hline \text{ADD $R_2,R_3$} & \text{$R2$} \leftarrow  \text{$R_2 + R_3$} & \text{$1$} \\\hline \text{MOV $6000,R_2$} & \text{Memory$[6000]$} \leftarrow  \text{$R_2$} & \text{$2$} \\\hline \text{HALT} & \text{Machine Halts} & \text{$1$} \\\hline \end{array}$$Consider that the memory is byte addressable with size $32$ bits, and the program has been loaded starting from memory location $1000$ (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

  1. $1007$
  2. $1020$
  3. $1024$
  4. $1028$
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HALT – It is a machine control instruction. It invokes unconditional jump with starting address of HALT as Target Address.

ex:- L1 : JMP L1

While execution of this instruction CPU enters into a infinite loop so reset operation required to run the new program.

I1 : 1000 – 1007

I2: 1008 – 1011

I3: 1012 – 1015

I4: 1016 – 1023

I5: 1024 – 1027  

 So, as we can see by diagram 1024 will be pushed onto the stack.

Answer : C                                             

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Consider that the memory is byte addressable with size 32 bits

Why are we considering the CPU WORD SIZE to be 32 bits from this above statement?

The term “WORD SIZE 32 bits” is nowhere mentioned.

We could have just thought of these 32 bits to be address bits of the memory.

Is the language used in the question standard?

Moreover it is said that the memory is said to be byte addressable.

The above quoted sentence simply does not convey the complete meaning to me.

Please help me...

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Question has a word missing – “Consider that the memory is byte addressable with ‘word’ size 32 bits”.
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edited by

@iamalokpandey, any single standard resource which supports whatever you have written about the HALT instruction. It seems like coming from some coaching notes where teacher made self-concepts. NO Single Standard Resource contains it Or supports it.

HLT Or Halt:

Stops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and SMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume execution. If an interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP) points to the instruction following the HLT instruction.

When a HLT instruction is executed on an Intel 64 or IA-32 processor supporting Intel Hyper-Threading Technology, only the logical processor that executes the instruction is halted. The other logical processors in the physical processor remain active, unless they are each individually halted by executing a HLT instruction.

The HLT instruction is a privileged instruction. When the processor is running in protected or virtual-8086 mode, the privilege level of a program or procedure must be 0 to execute the HLT instruction.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Source: https://www.felixcloutier.com/x86/hlt 

A special instruction, HALT, tells the CPU to stop executing altogether. If the instruction is the "halt" instruction, break out of the fetch/execute loop and exit the program. 

HALTHalt; stop execution of instructions.

Source: https://people.engr.tamu.edu/djimenez/classes/312-fall21/hw6/hw6.html 

During the fetch-decode-execute cycle, the PC would get incremented to the next instruction. The program instructions are executed sequentially until the HALT instruction which stops the program.

Source: https://www.cs.uni.edu/~fienup/cs041s11/lectures/Supplement_MARE_AL.pdf  

Usually after an instruction is executed, the program counter is increased by 1, and the whole "fetch-execute" cycle is repeated to execute the next instruction in memory. This process continues until a halt instruction is executed. 

The other CPU state consists of the program counter (or PC), which has 12 bits and holds the address of the next instruction to be executed, the run-flag, which is one bit and indicates whether the computer is running (1) or halted (0), and the arithmetic error bit (or AEB), which indicates whether there has been an arithmetic overflow error. 

halt -- stops execution (sets the run flag to 0) 

If the instruction that is executed is a halt instruction, all that happens is that the run flag (rf) is set to 0, and execution halts. 

Source: https://zoo.cs.yale.edu/classes/cs201/fall_2023/lectures/Architecture.html 

Program execution halts only if the machine is turned off, some sort of unrecoverable error occurs, or a program instruction(HALT) that halts the computer is encountered. (Source: William Stallings)

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4 Answers

101 votes
101 votes
Best answer

Option is D.

Word size is $32$ $bits$ ($4$ $bytes$). Interrupt occurs after execution of HALT instruction NOT during,  So address of next instruction will be saved on to the stack which is $1028$.  

(We have $5$ instructions starting from address $1000$, each of size $2, 1, 1, 2, 1$ totaling $7$ words $= 7 *4 =28$ $bytes$). 

$1000+ 28 = 1028$,

$1028$ is the starting address of NEXT Instruction .

After HALT instruction CPU enters a HALT state and if an interrupt happens the return address will be that of the instruction after the HALT. 

 References :

  1.  https://x86.puri.sm/html/file_module_x86_id_134.html [ X86 Instructors Manual ]
  2. http://electronics.stackexchange.com/questions/277735/what-happens-if-the-interrupt-occurs-during-the-execution-of-halt-instruction
  3. https://en.wikipedia.org/wiki/HLT_(x86_instruction)
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4 Comments

1024 should be correct answer
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I have a doubt. Memory starting address is given in decimal and size of total instruction is in bytes,then how decimal and bytes addition is taking place?
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Refer my comment HERE for several standard resources supporting the answer 1028. NOT a Single Standard Resource supports 1024. Students who are giving answer are following some poor coaching notes, not following the standard resources. 

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10 votes
10 votes
answer should be 1024 because consider the case where halt statement is succeeded by some AlU instructions now if you'll store the next intruction as the return address when an interrupt occur while executing halt then in that case after executing the interrupt program will execute those alu instruction which should not happen as program is already halted

2 Comments

True it is a valid case.
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@Sneha negi Ma'am, I understood from your answer that after HALT is executed no other instruction should be executed. But the below statement in the question 

after executing the HALT instruction, the return address will be...

Doesn’t it means now HALT has been executed and now its time for another instruction ?

Thanks in advance ! 

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6 votes
6 votes

It is clearly mentioned that HALT instruction has executed completely.

Now some other instruction just began its fetch at 1028, interrupt came, so it is bit OBVIOUS that 1028 will be the answer,

1007, 1020 are useless options

 

D is the corect answer

1 comment

No, HALT instruction changes the Program counter value to 1024, so that program remains halted until it is restarted again, so the PC value will remain 1024 which will be pushed onto the stack
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5 votes
5 votes

Working of HALT:

HALT instruction stops the execution of a program by changing the PC value to the current instruction program counter value (1028 is replaced with 1024 in this case) so when the HLT instruction is completed, the CPU fetches the instruction from the location specified in PC (PC contains 1024, ie HLT instruction) and increments the PC value to 1028 and does the same thing.

Now the fetched HALT instruction does the same thing again and again ( ie Changing the PC value to 1024 from 1028). It halts the program only from the user point of view, but HALT is simply busy waiting from the CPU point of view. 

So ans is 1024

 

PS: From Chottu’s comment "Interrupt comes during the halt instruction" and "Interrupt comes after halt instruction", both are the same. Because interrupt is served only after execution of current instruction.

Answer:

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