A $5-$ stage pipelined processor has IF,ID,EX,MEM and WB . WB stage operation is divided into two parts. In the first part register write operation and in second part register read operation is performed. The latency of those stages are $300,400,500,500,300$ (in nano seconds) respectively.Consider the following code executed on this processor, operand forwarding is used in the pipeline
Instruction No. |
Instruction |
Meaning of Instruction |
$I_{1}$ |
ADD $R_{3},R_{2},R_{4}$ |
$R_{3} <- R_{2} + R_{4}$ |
$I_{2}$ |
SUB $R_{6},R_{4},R_{3}$ |
$R_{6} <- R_{4} - R_{3}$ |
$I_{3}$ |
ADD $R_{7},R_{5},R_{3}$ |
$R_{7} <- R_{5} + R_{3}$ |
$I_{4}$ |
SUB $R_{1},R_{7},R_{4}$ |
$R_{1} <- R_{7} - R_{4}$ |
The program execution time__________ns?