After 3-clock pulses , what is the content of shift Register

Question

I could not understand here both the outputs point to D3 bit . How to proceed in this scenario ?

Answer 1

If we consider (clock + and) combination as a clock.

then after first clock o/p - 0101

now onwards the clock will always be 0.

2nd clock o/ - 0101

3rd clock o/p - 0101

hence, B

Comments

I think answer will be none

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why will the clock pulse be zero onwards?

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I mean the output of the AND gate.

Answer 2

OPTION (A)...

CLOCK     I/P       D3      D2     D1    D0

0                0       1         0            1        1

1               0        0         1             0         1

2               0        0         0            1          0

3               1         1         0             0         1

 

Hence the option 9A) is correct.