NIELIT 2017 July Scientist B (CS) - Section B: 23

Question

Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ?

• A. $T1=T2$
• B. $T1>T2$
• C. $T1<T2$
• D. $T1$ is $T2$ plus time taken for one instruction fetch cycle

Comments

Same question

https://gateoverflow.in/631/gate2000-1-8

But option B should be >=. It can be same if we there is no or negligible interstage delay.

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Option b is the correct one

Pipeline system contains interstage buffers registers that leads to delay if only one instructions we have to execute.

But in non-pipeline system we have no such registers so for only one instructions it will give better performance.

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Right

Answer 1

We assume that each stage takes ‘T’ unit of time both in pipelined and non-pipelined CPU.

Let total stages in pipelined CPU = Total stages in non-pipelined CPU = K 

 number of Instructions = N = 1

Pipelined CPU :

Total time (T1) = (K + (N – 1)) * T = KT

Non-Pipelined CPU :

Total time (T2) = KNT = KT

Considering buffer delays in pipelined CPU

Pipeline system contains interstage buffers registers that leads to delay if only one instructions we have to execute.

But in non-pipeline system we have no such registers so for only one instructions it will give better performance.

 T1 > T2

IF buffer delay is negligible in pipeline then T1=T2

so over all T1$\geqslant$T2

 Thus, option (B) is the answer.

Answer 2

if there is no delay then it will be t1=t2

but if we have delays  then it should be t1>t2

Answer 3

Pipelined CPUs are having interstage buffers that lead to additional delay. Therefore option B is correct.

T1>T2