NIELIT 2016 MAR Scientist C - Section C: 39

Question

 

If a clock with time period $“T”$ is used with $n$ stage shift register, then output of final stage will be delayed by

• A. $nT$ sec
• B. $(n-1)T$ sec
• C. $n/T$ sec
• D. $(2n-1)T$ sec

Answer 1

ANS : B

(n−1)T(n−1)T sec

Answer 2

take 4 register and initial data is 1011

ans bit are moving from MSB to LSB

1'st  2'nd  3'rd  4'rt

1     0      1       1  -initial data

1     1      0       1  -first shift

1     1      1       0  -second shift

0     1      1       1  -third shift

1     0      1       1  -initial data

option B

n-1 shift required

Answer 3

Ans b is correct

Because  shift register

Serial output n-1 times required