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A processor has $40$ distinct instruction and $24$ general purpose registers. A $32$-bit instruction word has an opcode, two registers operands and an immediate operand. The number of bits available for the immediate operand field is_______.
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16 bits .!
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Instruction Opcode Size $= \log_2 40 = 6$

Register operand size $= \log_224 =5$

Total bits available $= 32$

Bits required for opcode $+$ two register operands $= 6 + 2 \times 5 = 16$

Bits available for immediate operand $= 32 - 16 = 16.$
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rajinder singh

There are 40 opcodes, it means, there will be 40 distinct operations like ADD, SUB, MUL etc...So in order to represent one operation, we need some bits right!!! If we have 4 distinct operations like ADD, MUL, DIV, SUB, we have to represent each operation with some bits, here we need two bits.

00-ADD

01-MUL

10-DIV

11-SUB

So we need log24  = 2 bits

Similarly, in this question, we have 40 distinct opcodes, so in order to name them in binary

we need log240 = 6 bits

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But ln question they given  40 distinct instruction not 40 distinct operation then how you taken as 40 operation .If you think that it should be 40 operation then their might be chance that in 40distinct instructions  2 , 3 instruction can have same operation.
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But there will be a case when we get 40 distinct instructions where we distinguish each instruction by opcode field only so we need at least 6 bits for the opcode.
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Ans: 16

For 40 distinct instructions, you need atleast 6 bits for Opcode

For 24 distinct registers you need at least 5 bits to represent a single General purpose register.

So you can see in the image, I have explained the value of x. 

 

 

 

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log 40=6

log 24=5

6+5*2=16

32-16=16(answer)
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Answer : 16


For 40 distinct instructions : 

no. of bits need = Ceil (log(40)) =6

no. of bits need for 1 register =Ceil (log(24)) = 5

for another register = 5

for immediate operand :

no. of bits = 32-(6+5+5) = 16

6 5 5 16

op code       R1               R2          immediate

Answer:

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