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19981
My doubt
In connection termination of tcp....suppose client got the fin segment from server and and it send acknowledgment to server..and goes to time wait state...now suppose this acknowledgment is lost.....and server retransmit the fin segment to client which is in time wait ... my question is what will happen to client and server ....when they will go to closed state??? Please anyone explain....
Ritam Biswas 1
asked
in
Computer Networks
Oct 20, 2018
by
Ritam Biswas 1
187
views
0
votes
2
answers
19982
MadeEasy Test Series: Algorithms - Sorting
Consider the following scenario during insertion sort when the array looks like the following: {25,75,95,125,80,5,10} The number of comparisons that it will further take for the array to be completely sorted are______?
Somoshree Datta 5
asked
in
Algorithms
Oct 20, 2018
by
Somoshree Datta 5
1.6k
views
algorithms
sorting
made-easy-test-series
0
votes
1
answer
19983
Programming
Void Test (int arr[], int s, int e) { int temp; if(s >= e) return; temp = arr[s+1]; arr[s+1] = arr[e]; arr[e] = temp; Test(arr, s+1, e - 1) }
closed
Vikas Verma
asked
in
Programming in C
Oct 19, 2018
by
Vikas Verma
539
views
programming-in-c
0
votes
0
answers
19984
Basic programming
Can someone explain how value of i is evaluted step by step
closed
ranarajesh495
asked
in
Programming in C
Oct 19, 2018
by
ranarajesh495
191
views
0
votes
0
answers
19985
Data Structure
Given an array with n symbols, How many stack permutations possible?
Vikas Verma
asked
in
Programming in C
Oct 19, 2018
by
Vikas Verma
681
views
data-structures
0
votes
1
answer
19986
Error Control
Error Control is a mandatory service of A) Network Layer B) Transport Layer C) Session Layer D) Data Link Layer As far as I know, error control is mandatorily provided by both Transport Layer and Data Link Layer. Both B and D should be the answer?
garvit_vijai
asked
in
Computer Networks
Oct 19, 2018
by
garvit_vijai
1.1k
views
computer-networks
error-control
0
votes
0
answers
19987
Calculus
Deepalitrapti
asked
in
Mathematical Logic
Oct 19, 2018
by
Deepalitrapti
298
views
0
votes
0
answers
19988
Pushdown Automata
Sambhrant Maurya
asked
in
Theory of Computation
Oct 19, 2018
by
Sambhrant Maurya
737
views
pushdown-automata
theory-of-computation
dpda
0
votes
0
answers
19989
Shortest Remaining Time 1st
Calculate the percentage of CPU idle time.
Balaji Jegan
asked
in
Operating System
Oct 19, 2018
by
Balaji Jegan
928
views
0
votes
2
answers
19990
Set associative mapping
What is the number of multiplexers required in set associative mapping hardware ? Given set bits are S, tag bits are T and word bits are W.
Alakhator
asked
in
CO and Architecture
Oct 19, 2018
by
Alakhator
672
views
co-and-architecture
cache-memory
multiplexer
0
votes
1
answer
19991
made easy test series
Chetan28kumar
asked
in
Compiler Design
Oct 19, 2018
by
Chetan28kumar
441
views
compiler-design
code-optimization
three-address-code
numerical-answers
made-easy-test-series
0
votes
1
answer
19992
#k-map
what is cyclic prime implicant ?
Satbir
asked
in
Digital Logic
Oct 19, 2018
by
Satbir
355
views
digital-logic
3
votes
1
answer
19993
Programming execution doubt
#include<stdio.h> #define type int type foo(type b) { return b*b; } #undef type #define type float int main() { float a = foo(1.1); printf("%1.2f", a); } Please explain line by line execution of this program.
Mk Utkarsh
asked
in
Programming in C
Oct 19, 2018
by
Mk Utkarsh
875
views
programming-in-c
0
votes
1
answer
19994
Gate forum workbook
We are Simulate a cache of 16 words, 2-way set associate cache with 2 word cache lines and LRU replacement policy; assume the cache in initially empty. The following sequences of address references are generated (the addresses are given in hexadecimal), where all references are instruction ... (A) Set 1 contains 6A (B) Set 0 contains 108 (C) Both (A) and (B) (D) None of these
pream sagar
asked
in
CO and Architecture
Oct 19, 2018
by
pream sagar
352
views
co-and-architecture
cache-memory
gateforum-booklet
0
votes
0
answers
19995
Gate forum work book
Assume that we have three scenarios l. a fully associative cache, 2. a two way set associative cache and 3. a direct mapped cache. The cache size is 256 bytes. The cache line size is 8 bytes. All variables are 4 bytes. Assume that we have separate instruction and ... many data cache read misses will occur in Two-ay set associative cache? (A)11 (B) 19 (C) 35 (D) None of these
pream sagar
asked
in
CO and Architecture
Oct 19, 2018
by
pream sagar
413
views
co-and-architecture
cache-memory
least-recently-used
gateforum-booklet
0
votes
2
answers
19996
MADE EASY M
garimanand
asked
in
Mathematical Logic
Oct 19, 2018
by
garimanand
361
views
0
votes
0
answers
19997
MADE EASY
garimanand
asked
in
Operating System
Oct 19, 2018
by
garimanand
308
views
0
votes
1
answer
19998
MADE EASY CN
please explain this??
garimanand
asked
in
Computer Networks
Oct 19, 2018
by
garimanand
415
views
0
votes
1
answer
19999
MADE EASY MATHS
how to find eigen value using eigen vector
garimanand
asked
in
Mathematical Logic
Oct 19, 2018
by
garimanand
356
views
0
votes
0
answers
20000
MADE EASY COMPLILER
why second is not true please explain ??
garimanand
asked
in
DS
Oct 19, 2018
by
garimanand
195
views
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