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1

#Self doubt COA

Çșȇ ʛấẗẻ asked in CO and Architecture Feb 16

by Çșȇ ʛấẗẻ

307 views

1 vote

1 answer

2

Write regular expression to denote a language L a) String which begin or end with either 00 or 11. b) The set of all strings, when viewed as binary representation of integers, that are divisible by 2. c) The set of all strings containing 00. d) String not containing the substring 110.

M_Umair_Khan42900 asked in Theory of Computation Dec 29, 2022

by M_Umair_Khan42900

2.1k views

2 votes

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3

Applied Test Series
An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate effective address if the addressing mode of the instruction is Index with R1 as the index register.

LRU asked in CO and Architecture Oct 24, 2021

by LRU

889 views

3 votes

1 answer

4

Kurose and Ross Edition 6 Exercise 3 Question R7 (Page No 286)
Suppose a process in Host C has a UDP socket with port number 6789. Suppose both Host A and Host B each send a UDP segment to Host C with destination port number 6789. Will both of these segments be directed to the same ... Host C? If so, how will the process at Host C know that these two segments originated from two different hosts?

ajaysoni1924 asked in Computer Networks Apr 18, 2019

by ajaysoni1924

2.2k views

1 vote

1 answer

5

In a LAN network every system is identified by ?
In a LAN network every system is identified by (a) Name (b) MAC Address (c) IP Address (d) Serial number given by manufacturer the answer is given as IP address but according to me it should be MAC address.

*p asked in Computer Networks Feb 17, 2019

by *p

16.7k views

1 vote

0 answers

6

me test
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 2 MSS and the threshold at the start of 1 st transmission is 16 MSS. Assume TCP use over a lossy link i.e., timeout ... window at the start of slow start phase is 2 MSS ;so when timeout occur should'nt we start with window size of 2 MSS]

newdreamz a1-z0 asked in Computer Networks Jan 7, 2019

by newdreamz a1-z0

482 views

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7

made easy mock 1 q63
ANY BODY TRY OUT I GOT 4/11 = 0.36

CHïntän ÞäTël asked in CO and Architecture Jan 1, 2019

by CHïntän ÞäTël

392 views

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0 answers

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ME TEST
Consider Prof. Vamshi s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy used. If base address of array 'a is 0x0 and initially ... i] + a[1024* i]; what will be the physical memory size here?and how many bits should we assign for physical memory addressing?

newdreamz a1-z0 asked in CO and Architecture Dec 25, 2018

by newdreamz a1-z0

464 views

1 vote

1 answer

9

ME test series
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided ... the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825

newdreamz a1-z0 asked in CO and Architecture Dec 25, 2018

by newdreamz a1-z0

734 views

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0 answers

10

General doubt.
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz explain?

sushmita asked in CO and Architecture Dec 12, 2018

257 views

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0 answers

11

doubt
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate ... we use signed 2's complement instead of unsigned integer then what will be the maximum and minimum value of the immediate operand ?

night_fury asked in CO and Architecture Nov 25, 2018

495 views

1 vote

1 answer

12

Ace Test Series: Computer Networks - RSA Algorithm

Shankar Kakde asked in Computer Networks Nov 1, 2018

by Shankar Kakde

488 views

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0 answers

13

self doubt
Which addressing mode is best suited for runtime relocation. Which addressing mode is best suited for compile time relocation.

iamdeepakji asked in CO and Architecture Aug 4, 2018

224 views

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self doubt
Assume there are 34 different op-codes, 64 registers in the machine. Main memory size is 256 KB and number of addressing modes for each operand is 14. Every instruction has one source operand in register and another operand in memory. Find number of bits to encode an instruction. a). 38 b). 34 c). 32 d). 30

ds2905902 asked in CO and Architecture Jun 29, 2018

191 views

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15

Computing the average turnaround time using the multilevel queues
In a computing center there are four types of jobs according to their arrival times (in seconds), their priorities and their run times (in seconds); see the table below: -----------------Type 1------ ... - the higher the priority, the sooner they run) scheduling algorithm. [please use a quantum that provides short response time.]

ytr567 asked in Operating System Apr 11, 2018

by ytr567

791 views

1 vote

0 answers

16

Univeristy of California Finals
a) Assume each router implements FIFO queuing. If each flow consists of an identical, 1-Mbps constant bit rate UDP flow with equal packet sizes, what will the resulting rate be for each flow? You can assume that FIFO drops packets with uniform probability. ... is assigned a weight equal to its number (i.e., flow F4 gets weight 4). What are the resulting throughputs?

Balaji Jegan asked in Computer Networks Jan 29, 2018

by Balaji Jegan

367 views

1 vote

0 answers

17

Self knowlaged
Can we say any thing to computer if they haven't storage unit? Or First computer like abacas have storage unit ? What is current definition of computer:: My answer is : a system that have these 5 property is a computer::: 1.Electronic device ... Storage A person said this is wrong definition.. Then what is the current definition? And he said old computer hasn't storage unit

Harikesh Kumar asked in CO and Architecture Jan 18, 2018

by Harikesh Kumar

207 views

2 votes

0 answers

18

nptel course
why are WAR AND WAW hazards not possible in mips architecture please see this video at 17:58 youtube.com/watch?v=9mpOG9YtSLc&t=1242s

Venkat Sai asked in CO and Architecture Jan 5, 2018

272 views

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test book test series 2018
A virtual memory has a page size 1k words.there are 8 pages and 4 frames.associative memory page table contain following entries : page frame 6 0 1 1 4 2 0 3 which of following virtual address(decimal) will cause page fault? a)4098 b)5124 c)1022 d)6144

rohit vishkarma asked in CO and Architecture Nov 17, 2017

by rohit vishkarma

332 views

0 votes

1 answer

20

ace test series 2018

rohit vishkarma asked in Computer Networks Oct 31, 2017

by rohit vishkarma

416 views

8 votes

2 answers

21

Maximum and Minimum number in 16 bit Floating Point
16 bit Floating Point Representation $(-1)^{sign}*(1.M)*2^{Exp - 63}$ Sign = 1 bit Exponent = 7 bit Mantissa = 8 bit 1) Max positive number 2) Min positive number. 3) Max negative number. 4) Min negative number. 5) What is meant by precision.

Shubhanshu asked in CO and Architecture Sep 3, 2017

4.0k views

1 vote

0 answers

22

CN Network Security
Message digest provides only message authentication or can it provide user authentication also? MDC is a digest for message authentication.Can i also say MAC is also a digest for sender authentication?Please explain this

rahul sharma 5 asked in Computer Networks Aug 13, 2017

by rahul sharma 5

293 views

3 votes

2 answers

23

set associative cache
The physical address size on a machine is 36 bits.The number of tag bits in the physical address format in a 256 KB, 16 way block set associative cache is____bits. What will be the ans?

avinash41 asked in CO and Architecture Aug 9, 2017

775 views

0 votes

1 answer

24

Self Doubt
What is the meaning of processing time at source and destination? Under processing time what task happens?

Shubhanshu asked in Computer Networks Apr 21, 2017

248 views

1 vote

1 answer

25

RSA(self doubt)

gabbar asked in Computer Networks Apr 2, 2017

by gabbar

642 views

0 votes

1 answer

26

Ace CN question
An organization has a class C network and wants to form a subnet for four departments with hosts as follows: A:72 B:35 C:20 D:18 what is the possible arrangements? options: a) for A: 255.255.255.128 for B: 255.255.255.192 for C & D: 255.255. ... possible. so option A is not possible. But answer given is option A. I know i am lacking some concept here , please care to correct :)

vishwa ratna asked in Computer Networks Jan 12, 2017

by vishwa ratna

3.2k views

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27

Gate Practice Question
Assume bit error of 2*(10^-4).What maximum size block is possible if probability that a block containing an error is to be no longer than 10^-1 ?

Ravi_1511 asked in Computer Networks Dec 25, 2016

230 views

2 votes

1 answer

28

general conceptual doubt
Why increase in cache size doesnt affect conflict misses?? According to me when we will increase cache size number of blocks will increase and hence lesser no of conflicts will be there because less number of main memory blocks will contend for same cache line?? But its said that conflict miss is independent of cache size how?? This seems so confusing to me.

sushmita asked in CO and Architecture Dec 12, 2016

654 views

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Recent questions tagged computer