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Recent questions tagged digital-counter

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GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 59
For the circuit in the figure below, if the current state $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0$ is $6$ (in decimal) i.e. $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0=0110,$ then after the next positive edge of the clock signal the new state will be (in decimal)? (the flip-flops are positive edge triggered)

GO Classes asked in Digital Logic Jan 28

497 views

0 votes

1 answer

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GATE CS Mock 2018 | Question 60 | GFG
Consider the following statements regarding counters: S1 : The Hamming distance of an Overbeck counter is $1$. and the Hamming distance of a Johnson counter is $2$. S2 : Only output sequence $0, 8, 12, 14, 15, 7, 3, 1, 0, ...$ is possible in Overbeck counter ... S3 are false and S1 is true (C) Only S1, S3 are false and S2 is true (D) All S1, S2, and S3 are true

rajveer43 asked in Digital Logic Jan 12

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GFG CSE Mock 2018 | Sequential Circuits
Consider following counters: Counter-1: Counter-2: Which of the following option is correct? Counter-1 is a three-bit "counter" which counts $0, 1, 2, 4, 5, 7, 0, ... . $ ... $0, 1, 2, 3, 5, 6, 0, ... $.

rajveer43 asked in Digital Logic Jan 12

88 views

0 votes

1 answer

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made easy counters question

mudasirkhan asked in Digital Logic Dec 15, 2023

208 views

0 votes

1 answer

5

madeeasy booklet
How to solve this?

Sajal Mallick asked in Digital Logic Nov 20, 2023

by Sajal Mallick

248 views

0 votes

0 answers

6

madeeasy booklet
Here clr is active low that means 0 then it will clear to 0. Then (Q2.Q0)' =0 or Q2=1 and Q0=1 then clr works. Then it will contain only 1 state. Right?? But answer is different.

Sajal Mallick asked in Digital Logic Nov 20, 2023

by Sajal Mallick

119 views

0 votes

0 answers

7

ripple counter
In a 4-bit binary ripple counter, for every input clock pulse (a) All the flip-flops get clocked simultaneously. (b) Only one flip-flop get clocked at a time. (c) Two of the flip-flops get clocked at a time. (d) All the above statements are false.

someshawasthi asked in Digital Logic Jan 18, 2023

by someshawasthi

313 views

0 votes

0 answers

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self doubt
if i have given 2 flip flop clock simultaneously and 2 flip flop clock non simultaneously what is it synchronous counter or asynchronous counter ? why?

someshawasthi asked in Digital Logic Jan 18, 2023

by someshawasthi

281 views

0 votes

0 answers

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NIELIT 2021 Dec Scientist B - Section B: 2
Consider the following $2$ bit counter using $\text{T}$ flip-flops following $0-2-3-1-0$ sequence. What should be the value of $x$? $\text{Q}_{2}$ $\text{Q}_{1}+\text{Q}_{2}$ $\text{Q}_{1}\oplus \text{Q}_{2}$ $\text{Q}_{1}\oplus \overline{\text{Q}}_{2}$

admin asked in Digital Logic Jul 21, 2022

by admin

375 views

2 votes

1 answer

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GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 21
Consider the sequential circuit shown in the figure, where both flip-flops $\text{FD A}$ and $\text{FD B}$ used are positive edge-triggered $D$ flip-flops. The state of this circuit is represented by $(AB).$ This circuit is a $2$-bit complex ... $2.$ Number of PI for $D_{A}$ is $2$ and Number of EPI for $D_{B}$ is $3.$

GO Classes asked in Digital Logic Jun 2, 2022

255 views

2 votes

1 answer

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GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 22
Consider the sequential circuit shown in the figure, where both flip-flops $\text{FD A}$ and $\text{FD B}$ used are positive edge-triggered $D$ flip-flops. The state of this circuit is represented by $(AB).$ This circuit is a ... when $x=1$. It works as a down counter when $x=1$ and works as a johnson counter when $x=0$.

GO Classes asked in Digital Logic Jun 2, 2022

208 views

1 vote

1 answer

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GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 23
Consider the following circuit. What are the values of $P, Q, R$ after two cycles if $P=0, Q=1$ and $R=0$ to begin with? $011$ $101$ $100$ $111$

GO Classes asked in Digital Logic Jun 2, 2022

148 views

2 votes

1 answer

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GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 25
Consider the following circuit. $10011000010$ is supplied to the "data" terminal in $11$ clock cycles. After that the values of $q_2 q_1 q_0$ are $000$ $010$ $101$ $111$

GO Classes asked in Digital Logic Jun 2, 2022

254 views

0 votes

1 answer

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Made Easy Test Series Question
The frequency of the pulse at D is __________ Hz.

prnv28 asked in Digital Logic Dec 31, 2021

by prnv28

931 views

0 votes

0 answers

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Made Easy Test Series Question
The output frequency of a decade counter that is clocked from a 50 kHz signal is _________ kHz.

prnv28 asked in Digital Logic Dec 31, 2021

by prnv28

1.3k views

11 votes

3 answers

16

GATE CSE 2021 Set 1 | Question: 28
Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states? $011,101,000$ $001,010,111$ $011,101,111$ $001,010,000$

Arjun asked in Digital Logic Feb 18, 2021

by Arjun

7.1k views

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Recent questions tagged digital-counter