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Recent questions tagged dma
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1
COA - DMA
A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 500 MHz, and takes 500 and 1000 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 1 Kbytes, what is the percentage of processor time consumed for the transfer operation?________(Rounded off to three decimal)
ajayraho
asked
in
CO and Architecture
Nov 21, 2023
by
ajayraho
427
views
co-and-architecture
dma
interrupts
zeal-workbook
0
votes
1
answer
2
Gate
An I/O device transfers data at a rate of 10MB/s over a 100MB/S bus. The data is transferred in 4KB blocks. If the processor operates at 500MHz, and it takes a total of 5000 cycles to handle each DMA request, find the fraction of CPU time handling the data transfer with and without DMA.
Praful jha
asked
in
CO and Architecture
Jul 7, 2023
by
Praful jha
556
views
co-and-architecture
input-output
dma
3
votes
2
answers
3
I/O Modes | Process State Transition | COA & OS
MSQ A ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes? Synchronous I/O Asynchronous I/O Interrupt Driven I/O DMA
Souvik33
asked
in
CO and Architecture
Dec 2, 2022
by
Souvik33
745
views
operating-system
process-scheduling
co-and-architecture
dma
interrupts
input-output
multiple-selects
0
votes
1
answer
4
DMA
The below question is from Made Easy Test series The diagram shows single bus detached DMA configuration for a system. How many times system bus is used for single data transfer using DMA(Consider only data transfer, not command or status transfer) 1 2 3 0 Here answer ... My Doubt: In DMA their is direct data transfer from i/o to memory so system bus is accessed only once. Is this correct?
Chaitanya Kale
asked
in
CO and Architecture
Sep 24, 2022
by
Chaitanya Kale
1.3k
views
co-and-architecture
dma
made-easy-test-series
1
vote
2
answers
5
University Assignment
Question → Consider a system in which bus cycles take 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice-versa, takes 250 ns. One of the I/O devices has a data transfer rate of 50 KB/s and employs DMA. ... For how long would the device tie up the bus when transferring a block of 128 bytes? b)Repeat the calculation for cycle-stealing mode
lalitver10
asked
in
CO and Architecture
Sep 18, 2022
by
lalitver10
667
views
computer-peripherals
dma
moderate
9
votes
3
answers
6
GATE CSE 2022 | Question: 7
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput? $\text{DMA}$ based $\text{I/O}$ transfer Interrupt driven $\text{I/O}$ transfer Polling based $\text{I/O}$ transfer Programmed $\text{I/O}$ transfer
Arjun
asked
in
CO and Architecture
Feb 15, 2022
by
Arjun
5.0k
views
gatecse-2022
co-and-architecture
dma
1-mark
24
votes
3
answers
7
GATE CSE 2021 Set 2 | Question: 20
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ ... $\text{DMA}$, the data transfer rate of the device is __________ bits per second.
Arjun
asked
in
CO and Architecture
Feb 18, 2021
by
Arjun
11.1k
views
gatecse-2021-set2
numerical-answers
co-and-architecture
dma
1-mark
1
vote
1
answer
8
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 7 (Page No. 430)
One mode that some DMA controllers use is to have the device controller send the word to the DMA controller, which then issues a second bus request to write to memory. How can this mode be used to perform ... Discuss any advantage or disadvantage of using this method instead of using the CPU to perform memory to memory copy.
admin
asked
in
Operating System
Oct 28, 2019
by
admin
606
views
tanenbaum
operating-system
input-output
dma
descriptive
3
votes
1
answer
9
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 6 (Page No. 429 - 430)
Suppose that a system uses DMA for data transfer from disk controller to main memory. Further assume that it takes $t_{1}\: nsec$ on average to acquire the bus and $t_{2}\:nsec$ to transfer one word ... acquiring the bus to send one word and acknowledging a transfer also requires acquiring the bus to send one word.
admin
asked
in
Operating System
Oct 28, 2019
by
admin
1.2k
views
tanenbaum
operating-system
input-output
dma
descriptive
4
votes
2
answers
10
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 5 (Page No. 429)
A DMA controller has five channels. The controller is capable of requesting a $32$-bit word every $40\: nsec.$ A response takes equally long. How fast does the bus have to be to avoid being a bottleneck?
admin
asked
in
Operating System
Oct 28, 2019
by
admin
2.2k
views
tanenbaum
operating-system
input-output
dma
descriptive
1
vote
2
answers
11
Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 5 (Page No. 81)
On early computers, every byte of data read or written was handled by the CPU (i.e., there was no DMA). What implications does this have for multiprogramming?
admin
asked
in
Operating System
Oct 20, 2019
by
admin
1.8k
views
tanenbaum
operating-system
multi-programming
dma
descriptive
0
votes
0
answers
12
NPTEL assignment
A DMA controller transfers 32-bit words from an input device to memory in one clock cycle using cycle stealing. The input device transmits data at a rate of 9600 bytes per second. The CPU is fetching and executing instructions at an average rate of 2,000,000 instructions ... the DMA transfer by .. percent. I am getting 0.12 as the answer but they have given 0.24 please check
Utkarsh Joshi
asked
in
CO and Architecture
Jan 24, 2019
by
Utkarsh Joshi
942
views
co-and-architecture
dma
2
votes
3
answers
13
Ace Test Series: CO & Architecture - Instruction Execution
CPU can leave current instruction execution, without completing it for : Service of interrupt DMA Both Neither
Na462
asked
in
CO and Architecture
Jan 21, 2019
by
Na462
680
views
co-and-architecture
dma
ace-test-series
instruction-execution
0
votes
0
answers
14
AppliedAi MOCK1
An I/O device transfers a data 10MB/s over a bus which is capable of sending the data at a rate 100MB/s. Consider a processor operates at 200MHZ, and it takes 100 clock cycles to handle each DMA request. Suppose 8KB blocks of data has been transferred between I/O and main memory then calculate fraction of CPU time handling of the data transfer with DMA?
jatin khachane 1
asked
in
CO and Architecture
Jan 15, 2019
by
jatin khachane 1
630
views
co-and-architecture
dma
0
votes
0
answers
15
Self Doubt
Does DMA use interrupts? or not. please, someone ..
saif
asked
in
CO and Architecture
Jan 13, 2019
by
saif
286
views
co-and-architecture
dma
0
votes
0
answers
16
Made Easy Test Series
Consider a disk drive with the following specifications. 16 surfaces, 128 tracks / surfaces, 256 sectors / track, 512 B / sector, rotations speed 3600 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it ... each DMA cycle. Memory cycle time is 50microsec. The maximum percentage of time the CPU gets blocked during DMA operation is______?
Somoshree Datta 5
asked
in
CO and Architecture
Jan 11, 2019
by
Somoshree Datta 5
930
views
co-and-architecture
disk
dma
1
vote
1
answer
17
DMA doubt
For word preperatioin time what i thought is the time taken to transfer the data into DMA buffer is it correct ?. Or is any buffer is available inside DMA or not or that we are directly sending the data form disk to memory having a lot of doubt coming to this topic help please @Bikram @prashant sir.
chandan sahu
asked
in
CO and Architecture
Jan 9, 2019
by
chandan sahu
463
views
co-and-architecture
disk
dma
1
vote
0
answers
18
Percentage of CPU used in DMA burst mode
Wikipedia says this about DMA burst mode (https://en.wikipedia.org/wiki/Direct_memory_access#Burst_mode) In burst mode, an entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by ... . So should we consider this full duration as CPU consumed or just (bus grant time + bus release time)?
Raj Singh 1
asked
in
CO and Architecture
Jan 7, 2019
by
Raj Singh 1
527
views
co-and-architecture
dma
1
vote
0
answers
19
Cycle stealing mode when bus width is bigger than disk buffer
I was going through this problem: Consider a disk drive with the following specifications: 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode ... empty the disk buffer. And only after 4B are there in intermediate buffer, we send it over system bus.
Raj Singh 1
asked
in
CO and Architecture
Jan 7, 2019
by
Raj Singh 1
491
views
dma
co-and-architecture
0
votes
0
answers
20
ME Test
Shadan Karim
asked
in
CO and Architecture
Jan 7, 2019
by
Shadan Karim
212
views
co-and-architecture
disk
dma
1
vote
2
answers
21
DMA,interrupts
True/false 1. To access bus the DMA does not issue an interrupt it is done through DMA-request and DMA-acknowledge wires. Interrupt is issued by DMA to CPU only after complete data is transferred to the specific memory address by DMA. 2. DMA interrupts the CPU whenever it needs to initiate I/O and also when it has finished I/O transfers.
Gurdeep Saini
asked
in
CO and Architecture
Jan 4, 2019
by
Gurdeep Saini
1.0k
views
dma
co-and-architecture
interrupts
1
vote
0
answers
22
Made Easy Test Series
Assertion(A): The DMA technique is more efficient than the interrupt-driven technique for high volume I/O data transfer. Reason(R): The DMA technique doesnt make use of the interrupt mechanism. (a) Both A and R are true and R is the correct explanation of A. (b) Both A ... but R is not the correct explanation of A. © A is true but R is false. (d) A is false but R is true.
Somoshree Datta 5
asked
in
CO and Architecture
Dec 31, 2018
by
Somoshree Datta 5
2.1k
views
co-and-architecture
dma
assertion-reason
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