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Recent questions tagged memory
2
votes
2
answers
1
Gate Applied course Test series
What is answer for this question and also please explain the approach
Dheeraj Varma
asked
in
Operating System
Nov 16, 2021
by
Dheeraj Varma
1.2k
views
virtual-memory
operating-system
memory
memory-management
0
votes
0
answers
2
Andrew S. Tanenbaum (OS) Edition 4 Exercise 4 Question 7 (Page No. 333)
In some systems it is possible to map part of a file into memory. What restrictions must such systems impose? How is this partial mapping implemented?
admin
asked
in
Operating System
Oct 26, 2019
by
admin
383
views
tanenbaum
operating-system
file-system
memory
descriptive
2
votes
2
answers
3
UGC NET CSE | June 2019 | Part 2 | Question: 12
Suppose that the register $A$ and the register $K$ have the bit configuration. Only the three leftmost bits of $A$ are compared with memory words because $K$ has $1$'s in these positions. Because of its organization ... suited to parallel searches by data association. This type of memory is known as RAM ROM content addressable memory secondary memory
Arjun
asked
in
CO and Architecture
Jul 2, 2019
by
Arjun
2.3k
views
ugcnetcse-june2019-paper2
co-and-architecture
memory
1
vote
4
answers
4
UGC NET CSE | June 2019 | Part 2 | Question: 19
How many address lines and data lines are required to provide a memory capacity of $16 K \times 16$? $10, \:4$ $16, \: 16$ $14, \:16$ $4, \:16$
Arjun
asked
in
CO and Architecture
Jul 2, 2019
by
Arjun
8.3k
views
ugcnetcse-june2019-paper2
co-and-architecture
memory
0
votes
1
answer
5
self doubt-swap space
What is swap space in secondary memory?
Doraemon
asked
in
Operating System
Jun 5, 2019
by
Doraemon
356
views
secondary
memory
0
votes
2
answers
6
Computer Organisation
sidlewis
asked
in
CO and Architecture
Sep 12, 2018
by
sidlewis
911
views
co-and-architecture
dma
memory
0
votes
0
answers
7
MCQs in Computer Science -Timothy Williams 5 edition
A byte addressable computer has a memory capacity of 2^m kbytes and can perform 2^n operations. An instruction involving 3 operands and one operator needs a maximum of - (a) 3m bits (b) 3m+n bits (c) m+n bits (d) none of the above. Please provide a detailed explanation ...
DEEPAK PANDEY 1
asked
in
CO and Architecture
Apr 10, 2018
by
DEEPAK PANDEY 1
1.4k
views
co-and-architecture
memory
0
votes
1
answer
8
Variable Length Partition
Is it necessary that when we are doing a variable length partitioning the partition has to be created continuously i.e. For example I have $1000k$ of memory and i got two request for $120k$ and $120k$ then .... Is it must that i have to give two continuous ... $120K$s or I can also have such policy like:- $120k$ - Free Space- $120k$ - Free space i.e. Non continuous.
Na462
asked
in
Operating System
Mar 21, 2018
by
Na462
630
views
memory
0
votes
1
answer
9
Memory managment
Difference between static memory allocation and dynamic memory allocation.(Need concept clearing explanation)
Ahsanul Hoque
asked
in
Programming in C
Feb 28, 2018
by
Ahsanul Hoque
537
views
memory
memory-management
programming-in-c
2
votes
1
answer
10
Computer organisation
I know that correct answer is none of these But I need explanation with answer
Harikesh Kumar
asked
in
CO and Architecture
Jan 14, 2018
by
Harikesh Kumar
415
views
co-and-architecture
memory-interfacing
memory
0
votes
0
answers
11
UGC NET CSE | December 2009 | Part 2 | Question: 08
The highest noise margin is offered by $\text{BICMOS}$ $\text{TTL}$ $\text{ECL}$ $\text{CMOS}$
rishu_darkshadow
asked
in
Digital Logic
Sep 16, 2017
by
rishu_darkshadow
1.2k
views
ugcnetcse-dec2009-paper2
digital-logic
memory
0
votes
2
answers
12
Madeeasy test series
In a virtual memory system, size of virtual address is 40 bit, size of physical address is 32 bit, page size is 8 kb and size of each page table entry is 40 bit. Assume the main memory to be Byte addressable. The maximum number of bits that can be used for storing protection and other information in each page table entry are ___
gautamcse27
asked
in
Operating System
Dec 15, 2016
by
gautamcse27
1.3k
views
memory
memory-management
1
vote
1
answer
13
UGC NET CSE | September 2013 | Part 3 | Question: 32
A given memory chip has 14 address and 8 data pins. It has the following number of locations. $2^8$ $2^{14}$ $2^6$ $2^{12}$
go_editor
asked
in
CO and Architecture
Jul 24, 2016
by
go_editor
8.0k
views
ugcnetcse-sep2013-paper3
co-and-architecture
memory
0
votes
1
answer
14
UGC NET CSE | September 2013 | Part 3 | Question: 30
Which logic family dissipates the minimum power? DTL TTL ECL CMOS
go_editor
asked
in
CO and Architecture
Jul 24, 2016
by
go_editor
981
views
ugcnetcse-sep2013-paper3
co-and-architecture
memory
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