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Recent questions tagged multilevel-cache

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Cache Mapping
In a 2 level hierarchy, the cache has an access time of 15 ns and the main memory has an access time of 110 ns, the hit rate of the cache is 90%. If the block size of the cache is 16 Bytes, then average memory access time including miss penalty is?

Mrityudoot asked in CO and Architecture Jun 5, 2023

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2 votes

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2

cache miss question
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?

h4kr asked in CO and Architecture Dec 27, 2022

by h4kr

532 views

2 votes

1 answer

3

L1 and L2 cache
I have few doubts regarding $ L1$ and $ L2 $ cache Consider there is sequential access to L1 and L2 cache i.e L2 is accessed after L1 misses $\textup{Doubt 1:}$ Suppose we want to read data and data is not present in both $ L1$ and $ L2 $ then during reading ... do we write data only to $ L1$ or to both $ L1$ and $ L2 $? What happens if its said that both the cache are inclusive?

Chaitanya Kale asked in CO and Architecture Dec 12, 2022

by Chaitanya Kale

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1 vote

0 answers

4

Madeasy Test series

vishnu777 asked in CO and Architecture Nov 23, 2022

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5

Computer organisation cache
Why can't we have n-levels of cache ?

Priyansh Singh asked in CO and Architecture Jan 27, 2019

by Priyansh Singh

597 views

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1 answer

6

MadeEasy Test Series: CO & Architecture - Cache Memory
Consider the following statements: (i) Accessing of data in a column wise fashion maintains spatial locality only when the block size is equal to the total size of the elements in the row (ii) Coherence in write through protocol never occurs even cache memory is organized in multilevel. Which of the above is true?

Jay Bhutada 1 asked in CO and Architecture Jan 9, 2019

by Jay Bhutada 1

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7

UPPCL AE 2018:32
Which of the following statement is $\text{TRUE}$? Doubling the block size and halving the number of sets will reduce capacity misses The last-level cache is designed for high capacity rather than low latency Workloads with high temporal locality benefit from smaller cache block sizes Workloads with high spatial locality benefit from smaller cache block sizes

admin asked in CO and Architecture Jan 5, 2019

by admin

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8

CO madeeasy 2019 Multi level cache
please explain how hit ratio of L2 is taken as 0.5? instead of 0.9 as 10 misses are mentioned is it like as 20 misses at levle 1 out of which only 10 missed at level 2, so 10 out of 20 (and not 100) hence 0.5?

Markzuck asked in CO and Architecture Dec 21, 2018

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9

Calculating average access time in multi level cache
$h_1→L1$ hit ratio $h_2→L2$ hit ratio $C_1→ L1$ access time $C_2→ $Miss penalty to transfer information from L2 to L1 $M→$ Miss penalty to transfer information from main memory to L2 Average access time given in Carl Hamacher's book ... red. Is my equation correct or book's equation. Or something more is going on here, which I am unaware of?

Raj Singh 1 asked in CO and Architecture Dec 19, 2018

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conceptual doubt
in case of hierarchical memory organization when there is a miss in cache , we need to bring the entire block from main memory to cache so in the formula- AMAT= H1*T1+(1-H1(T1+T2)) T1- cache access time/word T2= memory access time/word T2 ... in some cases we just take word access time of main memory. also please tell me what should be T2 in case of simultaneous organization?

sushmita asked in CO and Architecture Dec 12, 2018

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11

cache
Consider a system with the average memory access time of a processor with one level (L1) cache is 2.8 clock cycles. If the required data is present in L1-cache it can be accessed in 1 clock cycle otherwise it needs 85 clock cycles to get it from memory. If another ... the access time of 6 clock cycles. What is the hit rate of L2-cache such that average memory access improved by 70%? (ans=71%)

Satbir asked in CO and Architecture Dec 6, 2018

by Satbir

229 views

1 vote

1 answer

12

miss penalty
Effective address time for a cache comprising of L1 and L2 cache =9ns hit ratio of L1 cache = 0.8 hit ratio of L2 cache = 0.9 memory access time =100ns Miss penalty of L1 cache = 25ns Access times for L1 and L2 caches are x and y ns; let z=x+y; what’s z?? I am getting 20.33 but the given answer is different!

Gate Fever asked in CO and Architecture Nov 28, 2018

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1 answer

13

cache memory
Consider a two-level memory hierarchy, L1 (cache) has an accessing time of 5 ns and main memory has an accessing time of 100 ns. Writing or updating contents takes 20 ns and 200 ns for L1 and main memory respectively. Assume L1 gives misses 20% ... instructions being read-only instructions. What is the average access time for the system (in ns) if it uses the WRITETHROUGH technique?

Shivangi Parashar 2 asked in CO and Architecture Nov 25, 2018

by Shivangi Parashar 2

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1 answer

14

Cache Memory
consider two-level cache hierarchies with L1 and L2 cache. Programs refer to memory 1000 times out of which 40 misses are in the L1 cache and 10 misses are in the L2 cache.If the miss penalty of L2 is 200 clock cycles,hit time of L1 is 1 clock cycle,and hit time of L2 is 15 clock cycles,the average memory access time is__________clock cycles.

Shivangi Parashar 2 asked in CO and Architecture Nov 25, 2018

by Shivangi Parashar 2

1.2k views

0 votes

1 answer

15

Gate forum Exam
In two level cache first level cache minimizes cache miss ratio , second level minimizes cache hit ratio . Explain .

kunal goswami asked in CO and Architecture Nov 17, 2018

by kunal goswami

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16

Self-doubt What events happen in Cache Access duration
What events happen when we say that a cache at level i is accessed? (I am able to use the cache formulas as given in textbooks and also most of the times, I arrive at the correct answer, but I want to fully understand the basic details ... duration? Do we include any extra time for STORING the data in the level (i-1)th cache as is done here ?

Harsh Kumar asked in CO and Architecture Sep 29, 2018

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17

Load Back Cache
In the memory access time formula for the hierarchical cache - which is given as :$Emat = H1\times T1 + (1-H1)(H2\times (T1+T2) + (1-H2)\times (T1+T2+T3))$ (where Hi = Hit Ratio for the i-th level cache and Ti = Access time for i- ... transferred into the cache. Is my intuition correct? If yes, then what should be the Emat formula for Load Back cache ? Should we add extra Ti values?

Harsh Kumar asked in CO and Architecture Sep 29, 2018

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Shiv Gaur asked in CO and Architecture Sep 13, 2018

183 views

1 vote

1 answer

19

performance of cache memory
in cache performace i have confusion about where to use which formula like for write through whether use H (tc) + (1-H) (tc+m) or H (tc) + (1-H) (m) and how to identify whether cache memory is hierarchical or not from question can anyone give me all formula related to cache performance with explanation

Rahul_Rathod_ asked in CO and Architecture Aug 6, 2018

by Rahul_Rathod_

600 views

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0 answers

20

performance cache exercise help
First level data cache: Direct mapping , writeThrough/write allocate , 8kb data and lines of 8 bytes, miss rate= 17% First level instructions cache: Direct mapping,, 4kb data and lines of 8 bytes, miss rate= 2% Second level unified cache: ... accesses to data memory and instructions of the total number of accesses? 5)What is the average memory access time? Thanks !!

mauro5991 asked in CO and Architecture Aug 2, 2018

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21

Cache Memory
Hi sir, i want to ask that how we'll come to know whether this is an independent memory organization or it is a hierarchical organization ? In case of hierarchical it's answer would've been 1.23T1 In case of independent it's answer is 1.11T1

Priyansh Singh asked in CO and Architecture Jul 2, 2018

by Priyansh Singh

278 views

–1 vote

1 answer

22

Carl Hamacher Cache Memory
What should be correct answer to this question? In solution it's option A in Carl hamacher text book it's B ? I am confused please help

vupadhayayx86 asked in CO and Architecture Jun 13, 2018

by vupadhayayx86

889 views

0 votes

1 answer

23

Cache memory
Consider a scenario, where there is 2 level cache in a memory hierarchy. 1)Now here if we take 1.4 memory accesses per instruction, that means if there are 100 instructions, then there will be 140 memory accesses. Here my question is how memory accesses can ... What miss rate is for L1,L2 and total in this memory hierarchy? Is it not number of misses in total number of instructions?

srestha asked in CO and Architecture Jun 10, 2018

668 views

3 votes

1 answer

24

Cache Memory
Consider the following statements: S1 : If capacity misses are most common then the designer should increase the cache associatively, in order to provide more flexibility when collision occurs. S2 : To hold the inclusion, lower level cache will be write through. Which of the statements are correct?

Harsh Mehta asked in CO and Architecture Jan 16, 2018

712 views

2 votes

0 answers

25

CO: Cache Memory

thepeeyoosh asked in CO and Architecture Jan 11, 2018

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1 answer

26

Comp.Architecture-3
My work: $1+0.1*5+0.05*50=4ns$ Now please give me reasoning about : missing in $L1$ i will access $L2$ and i did that now When i am missing in $L2$ isn`t this obvious that i have actually missed in $L1 $ or should i mention it by $0.05*0.1*50$ Thanks!

saxena0612 asked in CO and Architecture Dec 24, 2017

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27

co cache memory
if there is a miss in cache and hit in mm what is access time 60ns or 60+20=80ns. how is the statement " reference started again" related to the meaning of the question?

gari asked in CO and Architecture Nov 28, 2017

by gari

341 views

0 votes

2 answers

28

Confusion with a term
Can someone tell me what is the actual meaning of cache access / memory access time ? Is it the time to fetch a word/byte from cache or is it the time to search the cache or is it the sum of both? If it's the time to fetch a byte then why do we add this time in hierarchical access ? It's not the searching time right?

Xylene asked in CO and Architecture Jul 6, 2017

by Xylene

476 views

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Recent questions tagged multilevel-cache