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Recent questions tagged stall-cycle-per-instrution
10
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3
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Gateoverflow Computer architecture 2 exam question
Suppose there are 500 memory references in which 50 misses in the 1st level cache and 20 misses in the 2nd level cache . Let the miss penalty from L2 cache to memory is 100 cycles . Hit time in L2 cache is 20 cycles and hit ... per instruction will be __________ Ans is : 15 Can any explain how to solve this type of question, Thanks in advance.
hitendragarg001
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CO and Architecture
Dec 30, 2018
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hitendragarg001
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co-and-architecture
cache-memory
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