GATE CSE 2017 Set 2 | Question: 45

Question

The read access times and the hit ratios for different caches in a memory hierarchy are as given below:
$$\begin{array}{|l|c|c|} \hline \text {Cache} &  \text{Read access time (in nanoseconds)}& \text{Hit ratio} \\\hline \text{I-cache} & \text{2} & \text{0.8} \\\hline \text{D-cache} & \text{2} & \text{0.9}\\\hline \text{L2-cache} & \text{8} & \text{0.9} \\\hline \end{array}$$
The read access time of main memory in $90\;\text{nanoseconds}$. Assume that the caches use the referred-word-first read policy and the write-back policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always $0$ for all the blocks in the caches. In execution of a program, $60\%$ of memory reads are for instruction fetch and $40\%$ are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________

Comments

@Arjun Sir

I have a doubt when there is miss should we add previous access times

MAT = L1 Access Time + L1 Miss Rate [ L1 Access Time + L2 Access Time] + L1 Miss Rate * L2 Miss Rate[Memory Access time + L1 Access Time + L2 Access Time]

and

in which case we multiplied with hit rate as given in

https://www.geeksforgeeks.org/multilevel-cache-organisation/

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@Manu Thakur sorry for pointing out this typo error but sir it should be only two times 0.1 for operand fetch calculation. [Your approach is simple & elegant]

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why 3 times 0.1 is added in the question? @manu

Answer 1

• CPU connected to 2 caches (I cache and D cache) which are further connected to L2 cache and then Main Memory
• Referred-word-first read policy =>  no extra time to get the word from the fetched block
• In write-back policy ,a block is replaced if it is dirty (dirty bit 1) and is written back to main memory and in question dirty bit is 0 for all blocks so we do not care for writes.
• Direct mapped caches : Not relevant 

T_avg = 60% x T_Instr +  40% x T_operand

T_Instr = Hit ratio I cache x Time taken to access I cache  + Miss ratio of I cache  x Hit ratio L2 x Time taken to access L2 + Miss ratio of I cache x Miss ratio of L2 x Time taken to access Main memory 

        = (0.8*0.2) + (1-0.8)(0.9)(2+8) + (1-.08)(1-0.9)(2+8+90) = 5.4ns

T_operand  = Hit ratio D cache x Time taken to access D cache  + Miss ratio of D cache  x Hit ratio L2 cache x Time taken to access L2 cache+ Miss ratio of D cache x Miss ratio of L2 cache x Time taken to access Main memory 

        = (0.9*0.2) + (1-0.9)(0.9)(2+8) + (1-0.9)(1-0.9)(2+8+90)  = 3.7 ns

T_avg = (0.6)(5.4) +(0.4)(3.7) => 4.72 ns