Adding the corrected pipeline diagram for the question discussed in the video:
@Arjun Sir, you said in video that in True dependency consider the previous write only. I want to confirm that in Anti dependency and Output dependency can we consider out of order dependency?
@Arjun Sir, Please answer the above query. Please check is my understanding right?
R4 <- R1 + R4 R4 <- R2 + R4 R4 <- R4 + R5
there are following dependencies-
1) RAW(True) - (I1-I2) , (I2-I3) we'll not count (I1-I3) so 2.
2) WAR(Anti)- (I1-I2),(I1-I3) and(I2-I3) so 3.
3) WAW(Output) - (I1-I2),(I2-I3) and (I1-I3) so 3.
@Arjun Sir
in the video you told that WAR and WAW hazards cannot happen in an inorder pipeline..But in this link https://people.engr.ncsu.edu/efg/521/s06/common/lectures/notes/lec18.pdf
It is shown that WAR and WAW hazards can happen in an inorder pipeline also..where am I missing out?Can you pls explain Sir?
@Arjun Sir, if there is no data forwarding, why is the decode stage in I2 before WB in I1? (Same with decode in I4 before WB in I3). Won't the register files get old data in the decode stage? And if so, then how EX stage is getting the new if no forwarding is there?
Please help
@MiNiPanda, that is because of split phasing WB writes in first half cycle & ID reads operands in 2nd half of a clock cycle.
@Shubhgupta Okay so we can consider split phase at all times even if its not mentioned right? Thank you!! :)
Can you clear me one more thing.. why there is a RAW hazard b/w I2 and I4? I4 anyway have to wait for I3. So I2 isn't causing any extra stall.
@Shubhgupta
Please check my comment again. I have edited it.
@Arjun sir
Sir why we are not considering $IF$ stage of $I3$ from $3^{rd}$ clock cycle, which might lead to stalls if considered in such a way.
@Arjun sir i have the same doubt
@Shaik
@Mk Utkarsh Because $I_2$ hasn't started it's $ID$ phase yet. Observe that only when $I_2$ has started it's $ID$ phase in $5_{th}$ clock cycle, $I_3$ was able to start it's $IF$ phase during the same cycle.
@pranay562
If we consider table in such a way what is the problem we are facing. Please guide me where I am going wrong. Thanks.
As in CC3 as I1 start in the EX stage surely I2 will jump on ID stage as well as I3 will jump on IF stage. So where I am going wrong.
https://gateoverflow.in/753/gate2001-12
In this question which you have answered, you have taken $I3-I1$ as a RAW hazard. Why ? I think there is a RAW dependency b/w $I3-I1$ but that is not leading to hazard but because of $I2$ stalling it is effecting $I3$ also. And hence there is hazard between $I3-I1$.
But then why we are not considering $I3-I1$ hazard in this question which is similar case as of gate question ?
Sir me and kushagra discussed and have some doubt and i posted it here
https://csedoubts.gateoverflow.in/11532/pipelining-hazard-self-doubt
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