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User `JEET
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Answers by `JEET
1
vote
31
ISRO2020-71
Of the following, which best approximates the ratio of the number of nonterminal nodes in the total number of nodes in a complete $K$-ary tree of depth $N$ ? $1/N$ $N-1/N$ $1/K$ $K-1/K$
answered
in
DS
Jan 13, 2020
3.3k
views
isro-2020
data-structures
tree
normal
1
vote
32
ISRO2020-69
Consider the following pseudo-code I=0; J=0; K=8; while(I<K-1) //while-1 { J=J+1; while(J<K) //while-2 { if(x[I]<x[J]) { temp = x[I]; x[I]=x[J]; x[J]=temp; } }// end of while-2 I=I+1; }// end of while-1 The cyclomatic complexity of the above is $3$ $2$ $4$ $1$
answered
in
IS&Software Engineering
Jan 13, 2020
2.6k
views
isro-2020
is&software-engineering
cyclomatic-complexity
normal
5
votes
33
ISRO2020-4
Convert the pre-fix expression to in-fix $- ^{\ast} +ABC^{\ast} – DE+FG$ $(A-B)^{\ast}C+(D^{\ast}E)-(F+G)$ $(A+B)^{\ast}C-(D-E)^{\ast}(F+G)$ $(A+B-C)^{\ast}(D-E)^{\ast}(F+G)$ $(A+B)^{\ast}C-(D^{\ast}E)-(F+G)$
answered
in
DS
Jan 13, 2020
2.9k
views
isro-2020
data-structures
infix-prefix
normal
0
votes
34
ISRO2020-2
Statements associated with registers of a CPU are given. Identify the false statement. The program counter holds the memory address of the instruction in execution Only opcode is transferred to the control unit An instruction in the instruction register consists of the ... The value of the program counter is incremented by $1$ once its value has been read to the memory address register
answered
in
CO and Architecture
Jan 13, 2020
3.8k
views
isro-2020
co-and-architecture
control-unit
normal
2
votes
35
ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
answered
in
CO and Architecture
Jan 13, 2020
3.9k
views
isro-2020
co-and-architecture
normal
addressing-modes
0
votes
36
ISRO2020-22
Raymonds tree based algorithm ensures no starvation, but deadlock may occur in rare cases no deadlock, but starvation may occur neither deadlock nor starvation can occur deadlock may occur in cases where the process is already starved
answered
in
Databases
Jan 13, 2020
1.8k
views
isro-2020
databases
transaction-and-concurrency
normal
4
votes
37
ISRO2020-21
The master theorem assumes the subproblems are unequal sizes can be used if the subproblems are of equal size cannot be used for divide and conquer algorithms cannot be used for asymptotic complexity analysis
answered
in
Algorithms
Jan 13, 2020
2.7k
views
isro-2020
algorithms
master-theorem
easy
3
votes
38
ISRO2020-20
The minimum height of an AVL tree with $n$ nodes is $\text{Ceil } (\log_2(n+1))$ $1.44\ \log_2n$ $\text{Floor } (\log_2(n+1))$ $1.64\ \log_2n$
answered
in
DS
Jan 13, 2020
5.8k
views
isro-2020
data-structures
avl-tree
normal
3
votes
39
ISRO2020-19
What is the in-order successor of $15$ in the given binary search tree? $18$ $6$ $17$ $20$
answered
in
DS
Jan 13, 2020
2.1k
views
isro-2020
data-structures
binary-search-tree
easy
1
vote
40
ISRO2020-74
Following declaration of an array of struct, assumes size of byte, short, int and long are $1,2,3$ and $4$ respectively. Alignment rule stipulates that $n$ - byte field must be located at an address divisible by $n$, the fields in the struct are not rearranged, padding is used ... is located at an address divisble by $8$, what is the total size of $C$, in bytes? $150$ $160$ $200$ $240$
answered
in
Programming in C
Jan 13, 2020
3.3k
views
isro-2020
programming
normal
structure
0
votes
41
ISRO2020-75
A grammar is defined as $A \rightarrow BC$ $B \rightarrow x \mid Bx$ $C \rightarrow B \mid D$ $D \rightarrow y \mid Ey$ $E \rightarrow z$ The non terminal alphabet of the grammar is $\{A,B,C,D,E\}$ $\{B,C,D,E\}$ $\{A,B,C,D,E,x,y,z\}$ $\{x,y,z\}$
answered
in
Compiler Design
Jan 13, 2020
2.3k
views
isro-2020
compiler-design
grammar
parsing
easy
11
votes
42
ISRO2020-8
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is $8191$. How many registers the processor has? $32$ $64$ $128$ $16$
answered
in
CO and Architecture
Jan 13, 2020
3.8k
views
isro-2020
co-and-architecture
addressing-modes
normal
3
votes
43
ISRO2020-7
Consider a $5$- segment pipeline with a clock cycle time $20$ ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute $100$ instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) $5$ $4.03$ $4.81$ $4.17$
answered
in
CO and Architecture
Jan 13, 2020
7.3k
views
isro-2020
co-and-architecture
pipelining
normal
5
votes
44
ISRO2020-25
What is compaction refers to a technique for overcoming internal fragmentation a paging technique a technique for overcoming external fragmentation a technique for compressing the data
answered
in
Operating System
Jan 13, 2020
4.2k
views
isro-2020
operating-system
memory-management
easy
3
votes
45
ISRO2020-65
Of the following sort algorithms, which has execution time that is least dependant on initial ordering of the input? Insertion sort Quick sort Merge sort Selection sort
answered
in
Algorithms
Jan 13, 2020
3.4k
views
isro-2020
algorithms
sorting
normal
0
votes
46
ISRO2020-29
An aid to determine the deadlock occurrence is resource allocation graph starvation graph inversion graph none of the above
answered
in
Operating System
Jan 13, 2020
2.2k
views
isro-2020
operating-system
deadlock-prevention-avoidance-detection
easy
1
vote
47
ISRO2020-28
Dispatch latency is defined as the speed of dispatching a process from running to the ready state the time of dispatching a process from running to ready state and keeping the CPU idle the time to stop one process and start running another one none of these
answered
in
Operating System
Jan 13, 2020
4.2k
views
isro-2020
operating-system
process-synchronization
easy
2
votes
48
ISRO2020-27
Which of the following algorithms defines time quantum? shortest job scheduling algorithm round robin scheduling algorithm priority scheduling algorithm multilevel queue scheduling algorithm
answered
in
Operating System
Jan 13, 2020
5.9k
views
isro-2020
operating-system
process-scheduling
easy
12
votes
49
ISRO2020-63
What is the output in a $32$ bit machine with $32$ bit compiler? #include<stdio.h> rer(int **ptr2, int **ptr1) { int *ii; ii=*ptr2; *ptr2=*ptr1; *ptr1=ii; **ptr1*=**ptr2; **ptr2+=**ptr1; } void main(){ int var1=5, var2=10; int *ptr1=&var1,*ptr2=&var2; rer(&ptr1,&ptr2); printf("%d %d",var2,var1); } $60,70$ $50,50$ $50,60$ $60,50$
answered
in
Programming in C
Jan 13, 2020
3.9k
views
isro-2020
programming
programming-in-c
normal
pointers
14
votes
50
ISRO2020-62
What is output of the following ‘C’ code assuming it runs on a byte addressed little endian machine? #include<stdio.h> int main() { int x; char *ptr; x=622,100,101; printf("%d",(*(char *)&x)*(x%3)); return 0; } $622$ $311$ $22$ $110$
answered
in
Programming in C
Jan 13, 2020
5.7k
views
isro-2020
programming
programming-in-c
normal
pointers
4
votes
51
ISRO2011-40
Consider the following pseudocode x:=1; i:=1; while ( x <= 500) begin x:=2^x; i:=i+1; end What is the value of $\textsf{i}$ at the end of the pseudocode? $4$ $5$ $6$ $7$
answered
in
Algorithms
Jan 7, 2020
5.0k
views
isro2011
algorithms
identify-function
0
votes
52
ISRO2008-45
The TRAP is one of the interrupts available in $\textsf{INTEL 8085}.$ Which one of the following statements is true of TRAP ? it is level triggered it is negative edge triggered it is $\textsf{+ve}$ edge triggered it is both $\textsf{+ve}$ and $\textsf{-ve}$ edges triggered
answered
in
CO and Architecture
Jan 6, 2020
4.0k
views
isro2008
co-and-architecture
8085-microprocessor
non-gate
1
vote
53
ISRO2008-48
Which of the following is termed as minimum error code ? Binary code Gray code Excess-$3$ code Octal code
answered
in
Digital Logic
Jan 6, 2020
6.6k
views
isro2008
digital-logic
binary-codes
0
votes
54
ISRO2008-74
A Steiner patch is Biquadratic Bezeir patch Bicubic patch Circular patch only Bilinear Bezier patch
answered
in
Computer Graphics
Jan 6, 2020
2.6k
views
isro2008
non-gate
computer-graphics
1
vote
55
ISI2015-DCG-2
Let $S=\{6, 10, 7, 13, 5, 12, 8, 11, 9\}$ and $a=\underset{x \in S}{\Sigma} (x-9)^2$ & $b = \underset{x \in S}{\Sigma} (x-10)^2$. Then $a <b$ $a>b$ $a=b$ None of these
answered
in
Quantitative Aptitude
Jan 5, 2020
576
views
isi2015-dcg
quantitative-aptitude
summation
0
votes
56
ISRO2016-19
Consider a non-pipelined processor with a clock rate of $2.5$ gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to $2$ gigahertz. Assume ... no stalls in the pipeline. The speedup achieved in this pipelined processor is $3.2$ $3.0$ $2.2$ $2.0$
answered
in
CO and Architecture
Jan 5, 2020
6.0k
views
co-and-architecture
pipelining
isro2016
0
votes
57
GATE CSE 2006 | Question: 44
Station $A$ uses $32\; \text{byte}$ packets to transmit messages to Station $B$ using a sliding window protocol. The round trip delay between A and $B$ is $80\; \text{milliseconds}$ and the bottleneck bandwidth on the path between $A$ and $B$ is $128\; \text{kbps}$ . What is the optimal window size that $A$ should use? $20$ $40$ $160$ $320$
answered
in
Computer Networks
Jan 4, 2020
26.9k
views
gatecse-2006
computer-networks
sliding-window
normal
5
votes
58
ISRO2018-44
Station$A$ uses $32$ byte packets to transmit messages to Station $B$ using a sliding window protocol. The round trip delay between $A$ and $B$ is $80$ $ms$ and the bottleneck bandwidth on the path between $A$ and $B$ is $128$ $kbps$. What is the optimal window size that $A$ should use? $20$ $40$ $160$ $320$
answered
in
Computer Networks
Jan 4, 2020
2.9k
views
isro2018
computer-networks
sliding-window
2
votes
59
UGC NET CSE | January 2017 | Part 3 | Question: 26
Station $A$ uses $32$ byte packets t transmit messages to station $B$ using sliding window protocol. The round trip delay between $A$ and $B$ is $40$ milliseconds and the bottleneck bandwidth on the path between $A$ and $B$ is $64$ kbps. The optimal window size of $A$ is $20$ $10$ $30$ $40$
answered
in
Computer Networks
Jan 4, 2020
4.0k
views
ugcnetcse-jan2017-paper3
computer-networks
sliding-window
2
votes
60
ISRO2018-75
ln neural network, the network capacity is defined as: The traffic (tarry capacity of the network The total number of nodes in the network The number of patterns that can be stored and recalled in a network None of the above
answered
in
Artificial Intelligence
Jan 3, 2020
2.6k
views
isro2018
non-gate
neural-network
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