ISRO-DEC2017-71

Question

A $32$-$bit$ adder is formed by cascading $4$-$bit$ CLA adder.The gate delays (latency)
for getting the sum bits is

• A. $16$
• B. $18$
• C. $17$
• D. $19$

Comments

18 gate delay

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Check out this full diagram:

img source: https://www.electricaltechnology.org/

Full 4-bit CLA schematic diagram

Now similar to above CLA  there are a total of 8 such CLAs.

CarryLookahead block for 1st CLA takes 2 T_gd (Time for gate delay) in total. C4 is fed to the input of next carry-lookahead block of 2nd CLA and so on. Thus total T_gd (SUM) = 1 (P&G generator) + 2*8 + 1 (SUM adder) = 18.

T_gd (CARRY) = T_gd (SUM) + 2.

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Tuhin Dutta

It should be 7*3 + 4 = 25 gate delays, If I take every gate has 1 delay unit.

It's kind of Hybrid adder.

8 CLA & between them there are 7 gaps(like RLA). each CLA will pass carry to it's adjacent CLA.

carry generate in each CLA will take 3 gate delays & at last, sum will generate in 4 gate delays.

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Each 4-bit CLA adder has a fixed propagation delay, typically a few gate delays. Let's assume it's 3 gate delays for simplicity

Cascading 4-bit CLA adders to form a 32-bit adder introduces additional delays for carry propagation between stages.

To calculate the total delay:

• Count the number of 4-bit CLA adders in the chain: 32 bits / 4 bits/adder = 8 adders.
• Each adder's carry output is used as the carry input for the next adder, adding a delay.
• For 8 adders, there are 8-1 = 7 carry propagation delays between stages.
• Total delay = Delay of first 4-bit CLA + Carry propagation delays + Delay of last 4-bit CLA
• Total delay = 3 + 7 + 3 = 13
•  
• Ripple Effect Delay:
  • To produce the final sum bits, the carry from the last 4-bit CLA must propagate through the sum logic of the previous stages.
  • This adds approximately 5 more gate delays.
  •  
• Therefore, the total gate delays (latency) for getting the sum bits in a 32-bit adder formed by cascading 4-bit CLA adders is approximately 13 + 5 = 18.

Answer 1

A 32 bit adder is formed by  cascading 4 bit CLA adder means 8 4 bit CLA are in one after another in sequence manner.In first,4 bit CLA circuit diagram as you can see that all data are present (A0 A1 A2 A3, B0 B1 B2 B3,C0 also) so for C4 it will take 3 cycles and Sum bits(S0 S1 S2 S3) take 1 more cycles. In this extra 1 cycles C4 will move to next CLA circuit and  make output C5 in 5 cycles and so on.So ,total gate delays=(1st +2nd+3rd+4th+5th+6th+7th+8th)=(3+2+2+2+2+2+2+3)=18 cycles.

If anyone have any doubt please ask me.

Comments

Why is c4 taking 3 cycles?

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I too have the same doubt as above two doubts. Please help.

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Can you provide any video lecture or any kind of source to understand these kind of questions well

Thanks in Advance.

Answer 2

​​​​​​8 four bit CLA are needed to create a 32 bit Adder 

P & G Generator  will take 1 gate delay (as EXOR and AND will operate in parallel) 

Carry generator will take 2 Gate delays (All AND in parallel (1)+All ORs in Parallel(1)=2)

C4 will be available to next CLA and next CLA will Take 2 gate delays also . During same time Sum Generator of first will calculate sums not taking any extra time 

same thing will happen for all 8 carry generators 2*8=16 .During the same time 7 Sum generators will calculate sum without taking extra time as all are working in parallel

Sum generator of last CLA will take 1 gate delay (all EX-or in parallel)

total 1+2*8+1=18

Answer option B

 

Answer 3

18 gate delay

Comments

Explain

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I can't understand how to solve these type of questions