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Recent questions and answers in Digital Logic
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Recent questions and answers in Digital Logic
0
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NIELIT 2016 DEC Scientist B (IT) - Section B: 45
Which will be the equation of simplification of the given K-map? $AB' + B'CD' + A'B'C'$ $AB' + A'B'D' + A'B'C'$ $B'D' + AB' + B'C'$ $B'D' + A'B'C' + AB'$
answered
May 7
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Digital Logic
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abhishek tiwary
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46
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nielit2016dec-scientistb-it
0
votes
2
answers
2
50
views
NIELIT 2016 DEC Scientist B (CS) - Section B: 33
What will be the Excess-$3$ code for $1001$? $1001$ $1010$ $1011$ $1100$
answered
May 5
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Digital Logic
by
abhishek tiwary
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50
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nielit2016dec-scientistb-cs
0
votes
1
answer
3
42
views
NIELIT 2016 DEC Scientist B (IT) - Section B: 53
What is $2$'s complement of $(101)_3$ ? $(010)_3$ $(011)_3$ $(121)_3$ $(121)_2$
answered
May 5
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Digital Logic
by
abhishek tiwary
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42
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nielit2016dec-scientistb-it
0
votes
1
answer
4
186
views
Digital Design by Morris Mano
4.11 Using four half-adders (HDL-see Problem 4.52), (a) Design a full-subtractor circuit incrementer. (A circuit that adds one to a four-bit binary number.) (b) Design a four-bit combinational decrementer (a circuit that subtracts 1 from ... form, so is it possible to design the circuit using only four half adders if we assume the number is in Unsigned Representation?
answered
May 4
in
Digital Logic
by
shubham02
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221
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186
views
+3
votes
4
answers
5
201
views
ISI2017-DCG-10
The value of the Boolean expression (with usual definitions) $(A’BC’)’ +(AB’C)’$ is $0$ $1$ $A$ $BC$
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May 3
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Digital Logic
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DIBAKAR MAJEE
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201
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isi2017-dcg
digital-logic
boolean-algebra
boolean-expression
+8
votes
6
answers
6
5.5k
views
ISRO2015-7
If half adders and full adders are implements using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be 0,17 16,1 1,16 8,8
answered
May 3
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Digital Logic
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Pradosh123
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17
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5.5k
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isro2015
digital-logic
adder
+2
votes
4
answers
7
1k
views
UGCNET-Dec2014-II-06
The $BCD$ adder to add two decimal digits needs minimum of $6$ full adders and $2$ half adders $5$ full adders and $3$ half adders $4$ full adders and $3$ half adders $5$ full adders and $2$ half adders
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May 1
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Digital Logic
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221
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1k
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ugcnetdec2014ii
digital-logic
adders
+1
vote
4
answers
8
5.1k
views
the mimimum no of 2-input nand gates required to implement th function F=(x'+y')(z+w)?
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Apr 27
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Digital Logic
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DIBAKAR MAJEE
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+4
votes
4
answers
9
1.8k
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What is the value of base x?
Given $(135)_x+(144)_x=(323)_x$ What is the value of base $x$ ?
answered
Apr 27
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Digital Logic
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DIBAKAR MAJEE
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number-representation
+18
votes
5
answers
10
3.4k
views
GATE2016-1-30
Consider the two cascade $2$ to $1$ multiplexers as shown in the figure . The minimal sum of products form of the output $X$ is $\overline{P} \ \overline {Q}+PQR$ $\overline{P} \ {Q}+QR$ $PQ +\overline{P} \ \overline{Q}R$ $\overline{Q} \ \overline{R} + PQR$
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Apr 27
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Digital Logic
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gate2016-1
digital-logic
multiplexer
normal
+77
votes
13
answers
11
19.4k
views
GATE2016-1-8
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.
answered
Apr 27
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Digital Logic
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gate2016-1
digital-logic
digital-counter
flip-flop
normal
numerical-answers
0
votes
2
answers
12
460
views
After 3-clock pulses , what is the content of shift Register
I could not understand here both the outputs point to D3 bit . How to proceed in this scenario ?
answered
Apr 27
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Digital Logic
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DIBAKAR MAJEE
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digital-logic
+5
votes
3
answers
13
1.5k
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The number of possible boolean functions that can be defined for n boolean variables over n valued boolean algebra is
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Apr 27
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Digital Logic
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digital-logic
boolean-algebra
0
votes
2
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14
322
views
MadeEasy Workbook: Digital Logic - Synchronous Asynchronous Circuits
answered
Apr 27
in
Digital Logic
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DIBAKAR MAJEE
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322
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digital-logic
synchronous-asynchronous-circuits
made-easy-booklet
0
votes
1
answer
15
27
views
UGCNET-Dec2004-II: 10
The characteristic equation of a T flip-flop is : $Q_{n+1}=T\overline Q_n+\overline T Q_n$ $Q_{n+1}=T+Q_n$ $Q_{n+1}=TQ_n$ $Q_{n+1}=\overline T$\overline Q_n$ The symbols used have the usual meaning.
answered
Apr 25
in
Digital Logic
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Sabirazain
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201
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27
views
ugcnetdec2004ii
0
votes
1
answer
16
28
views
NIELIT 2016 DEC Scientist B (CS) - Section B: 35
What will be the final output of D flip-flop, if the input string is $11010011$? $1$ $0$ Don’t Care None of the above
answered
Apr 25
in
Digital Logic
by
Sabirazain
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201
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28
views
nielit2016dec-scientistb-cs
0
votes
1
answer
17
29
views
NIELIT 2016 DEC Scientist B (IT) - Section B: 59
The Decimal equivalent of the Hexadecimal number $(AC7B)_{16}$ is: $32564$ $44155$ $50215$ $43562$
answered
Apr 24
in
Digital Logic
by
Sabirazain
(
201
points)
29
views
nielit2016dec-scientistb-it
0
votes
1
answer
18
35
views
NIELIT 2016 DEC Scientist B (IT) - Section B: 58
How many addition and subtraction are required if you perform multiplication of $5$(Multiplicand) and $-30$(Multiplier) using Booth algorithm? $2,1$ $1,2$ $1,1$ $2,2$
answered
Apr 24
in
Digital Logic
by
Sabirazain
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201
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35
views
nielit2016dec-scientistb-it
+57
votes
3
answers
19
61k
views
Minimum NAND/NOR Gates - Realization for ExOR,ExNor,Adder,Subtractor
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?
answered
Apr 19
in
Digital Logic
by
RoyArun
(
27
points)
61k
views
0
votes
2
answers
20
92
views
NIELIT 2016 MAR Scientist B - Section C: 2
In which of the following adder circuits, the carry look ripple delay is eliminated? Half adder Full adder Parallel adder Carry-look ahead adder.
answered
Apr 19
in
Digital Logic
by
RoyArun
(
27
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92
views
nielit2016mar-scientistb
+1
vote
3
answers
21
131
views
NIELIT 2016 MAR Scientist B - Section C: 1
Which of the following logic expression is incorrect? $1\oplus0=1$ $1\oplus1\oplus0=1$ $1\oplus1\oplus1=1$ $1\oplus1=0$
answered
Apr 19
in
Digital Logic
by
RoyArun
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27
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131
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nielit2016mar-scientistb
+1
vote
1
answer
22
84
views
Gateforum Test Series: Digital Logic - Prime Implicants
Clearly, there will be two essential prime implicants. Why answer is 3?
answered
Apr 18
in
Digital Logic
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varunraj
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gateforum-test-series
digital-logic
prime-implicants
0
votes
1
answer
23
50
views
NIELIT 2016 DEC Scientist B (CS) - Section B: 45
What will be the equation of the given K-map? $A’B’D’+C’D+AB’C’$ $B’CD’+AB’C’+A’C’$ $B’D’+C’D$ $C’D+B’CD’$
answered
Apr 15
in
Digital Logic
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455
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50
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nielit2016dec-scientistb-cs
0
votes
1
answer
24
54
views
NIELIT 2016 DEC Scientist B (IT) - Section B: 33
How many inputs are required in Full Adder Circuit? $2$ $3$ More than two inputs None of the above
answered
Apr 15
in
Digital Logic
by
debasree88
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455
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54
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nielit2016dec-scientistb-it
0
votes
1
answer
25
67
views
NIELIT 2016 MAR Scientist B - Section C: 3
The output of a sequential circuit depends on present inputs only. past inputs only. both present and past inputs. present outputs only.
answered
Apr 15
in
Digital Logic
by
debasree88
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455
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67
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nielit2016mar-scientistb
0
votes
1
answer
26
111
views
Morris Mano Edition 3 Exercise 2 Question 18 (Page No. 71)
Show that the Dual of the Exclusive OR is equal to its complement.
answered
Apr 14
in
Digital Logic
by
debasree88
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455
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111
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digital-logic
morris-mano
boolean-algebra
+3
votes
2
answers
27
386
views
GATE1991-06,a
Using D flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines: Clock $\text{CLK}$ Three parallel data inputs $A, B, C$ Serial input $S$ Control input $\text{load} / \overline{\text{SHIFT}}$.
answered
Apr 12
in
Digital Logic
by
Pradip13
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19
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386
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gate1991
digital-logic
difficult
unsolved
+10
votes
3
answers
28
3.2k
views
ISRO2016-8
The minimum Boolean expression for the following circuit is AB+AC+BC A+BC A+B A+B+C
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Apr 6
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Digital Logic
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isro2016
digital-logic
boolean-algebra
+8
votes
2
answers
29
5.4k
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ISRO2016-7
The minimum number of NAND gates required to implement the Boolean function $A + A\bar{B} + A\bar{B}C$ is equal to 0 (Zero) 1 4 7
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Apr 6
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Digital Logic
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immanujs
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isro2016
+11
votes
7
answers
30
4.9k
views
ISRO2016-16
The simplified SOP (Sum of Product) from the Boolean expression $(P + \bar{Q} + \bar{R}) . (P + {Q} + R) . (P + Q +\bar{R})$ is $(\bar{P}.Q+\bar{R})$ $(P+{Q}.\bar{R})$ $({P}.\bar{Q}+R)$ $(P.Q+R)$
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Apr 6
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digital-logic
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isro2016
+7
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5
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31
2.1k
views
ISRO-2013-28
The most simplified form of the Boolean function $x (A, B, C, D) = \sum (7, 8, 9, 10, 11, 12, 13, 14, 15)$ (expressed in sum of minterms) is? A + A'BCD AB + CD A + BCD ABC + D
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Apr 6
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isro2013
digital-logic
canonical-normal-form
0
votes
2
answers
32
66
views
NIELIT 2016 MAR Scientist B - Section C: 7
How many RAM chips of size $(256K \times 1 bit)$ are required to build $1M\:Byte$ memory? $8$ $10$ $24$ $32$
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Apr 4
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nielit2016mar-scientistb
+17
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5
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33
6.6k
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GATE2009-7, ISRO2015-3
How many 32K $\times$ 1 RAM chips are needed to provide a memory capacity of 256K-bytes? 8 32 64 128
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Apr 4
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gate2009
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easy
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isro2015
0
votes
1
answer
34
57
views
NIELIT 2017 July Scientist B (CS) - Section B: 19
To make the following circuit a tautology marked box should be? OR gate AND gate NAND gate EX-OR gate
answered
Apr 4
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nielit2017july-scientistb-cs
0
votes
1
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35
32
views
NIELIT 2017 July Scientist B (CS) - Section B: 20
In the following gate network which gate is redundant? Gate no.$1$ Gate no.$2$ Gate no.$3$ Gate no.$4$
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Apr 3
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nielit2017july-scientistb-cs
0
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2
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36
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NIELIT 2017 July Scientist B (CS) - Section B: 17
The digital multiplexer is basically a combination logic circuit to perform the operation AND-AND OR-OR AND-OR OR-AND
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Apr 3
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Digital Logic
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nielit2017july-scientistb-cs
0
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1
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37
46
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NIELIT 2017 July Scientist B (CS) - Section B: 21
The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent? NOT OR AND XOR
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Apr 3
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nielit2017july-scientistb-cs
0
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38
44
views
NIELIT 2017 July Scientist B (CS) - Section B: 18
In digital logic, if $A\oplus B=C$, then which one of the following is true? $A\oplus C=B$ $B\oplus C=B$ $A\oplus B\oplus C=0$ Both A and B
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Apr 3
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nielit2017july-scientistb-cs
0
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1
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39
36
views
NIELIT 2016 DEC Scientist B (CS) - Section B: 59
The Decimal equivalent of the Hexadecimal number $(A09D)_{16}$ is $31845$ $41117$ $41052$ $32546$
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Apr 3
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Digital Logic
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+2
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1
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40
448
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Digital Logic: GATE 2013 EE
The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is ‘0’, then the frequency of the output waveform Q in kHz is 0.25 0.5 1 2
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Apr 2
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flip-flop
digital-logic
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