GATE IT 2006 | Question: 79

Question

A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement $X = (S - R * (P + Q))/T$ is given below. The values of variables $P, Q, R, S$ and $T$ are available in the registers $R0, R1, R2, R3$ and $R4$ respectively, before the execution of the instruction sequence.

$$\begin{array}{lll}  \text{ADD} & \text{$R5,R0,R1$} & \text{$;R5$} \leftarrow \text{R0 + R1} \\
\text{MUL}& \text{$R6,R2,R5$} & \text{$;R6$} \leftarrow \text{R2 * R5} \\
 \text{SUB} &  \text{$R5,R3,R6$} & \text{$;R5$} \leftarrow \text{R3 -R6}  \\ 
\text{DIV} &\text{$R6,R5,R4$} & \text{$;R6$} \leftarrow \text{R5/R4} \\
\text{STORE} &\text{$R6,X$}& \text{$;X$} \leftarrow \text{R6}  \\
\end{array}$$

The IF, ID and WB stages take 1 clock cycle each. The EX stage takes $1$ clock cycle each for the ADD, SUB and STORE operations, and $3$ clock cycles each for MUL and DIV operations. Operand forwarding from the EX stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is

• A. $10$
• B. $12$
• C. $14$
• D. $16$

Comments

Please someone change the direction of arrows in the instructions shown in this question.

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It's $4-$ stage pipeline.  Memory access phase of RISC architecture is implicitly included in $EX$ stage so split phase can be safely assumed.

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similar

https://gateoverflow.in/1235/gate2007-37-isro2009-37

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Can anyone please confirm whether @2019_Aspirant comment is true or not ?

Because what I know is split phase is independent of operand forwarding and split phase doesn’t depend on any architecture (in accordance to the GATE PYQ’s solved). We can safely use split-phase here irrespective of whether it’s mentioned that operand forwarding is used or not. Another point is I have read that operand forwarding needs independent cycles to occur, unlike split-phase wherein a single cycle (using rising edge and falling edge) we can implement it(split phase). So, what I think is that this question has no significance of the line operand forwarding because if it’s mentioned or not, still we will use the split-phase, which gives us the required result. @Arjun Sir, @Bikram Sir.

Answer 1

Hazards in computer architecture are events that cause delays in the pipeline and prevent an instruction from being executed in the designated clock cycle.

If there is no any types of hazard then :-

Number of clock cycles = K+n-1 , where K :  No. of stages, n: No. of instructions

                                       =4+5-1

                                        =8

There are 3 types of hazards in pipeline system : 1.Structural 2.Data 3.Control

Extra cycle due to hazards :-

1.Structural:  MUL and  DIV operations takes 3-1 = 2  extra cycles each i.e 2*2=4.

2.Data :  There is no extra cycles due to data hazard because of operand-forwarding(Given in question)

3.Control : Since, There is no branch instruction therefore no extra cycles due to control hazard

NOW,

The number of clock cycles required to complete the sequence of instructions is = 8+4 = 12.