GATE CSE 2023 | Question: 32

Question

A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected to the chip select $\text{(CS)}$ port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from $\text{IA11-IA0}$ are connected to the address port of these blocks. The chip select $\text{(CS)}$ is active high.

The input memory addresses $\text{(IA11-IA0)},$ in decimal, for the starting locations $\text{(Addr = 0)}$ of each block (indicated as $\text{X1, X2, X3, X4}$ in the figure) are among the options given below. Which one of the following options is $\text{CORRECT}?$

• A. $(0,1,2,3)$
• B. $(0,1024,2048,3072)$
• C. $(0,8,16,24)$
• D. $(0,0,0,0)$

Comments

@amitarp818 no the answer will still be the same

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if the Decoder were active low, then the Decoder behaviour would not exactly suit the purpose of Address expandsion of ram, as you can see the truth table of active low vs active high decoders here. https://www.tutorialspoint.com/decoder-for-active-low-and-high-output

PS: not talking about the active high vs active low in chip set. sry

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so much details are given about vertical arrangement but the trick is that we should not go with Option B as mostly we can make mistake by considering the question as high order memory interleaving.As it's clearly given that A4A3 are used for chip select

Answer 1

A 4 KB memory is given. 

4 KB = $2^{12}$, means we require 12 bits for its representation. But, 4 KB memory is implemented as four 1 KB

memory blocks.

Out of these 12 bits, 2 bits(I4 & I3) are connected to 2:4 Decoder. 

4 output pins of decoder Q0, Q1, Q2, Q3 is connected to 4 chip select ports of X1, X2, X3 & X4 respectively.

With 2-bits we can generate 4 different configurations, which are sufficient to uniquely identify the memory block.

Q0, Q1, Q2, Q3 can be recognized by these corresponding values of I4 & I3 :

I4	I3	O/p
0	0	Q0
0	1	Q1
1	0	Q2
1	1	Q3

 

Remaining 10 bits are connected to address port of these blocks.

For starting location (Addr =0) we have to put all the bits from I0 – I11 as 0.

I11	I10	I9	I8	I7	I6	I5	I4	I3	I2	I1	I0	Addr=0	Decimal Val.
0	0	0	0	0	0	0	0	0	0	0	0	X1	0
0	0	0	0	0	0	0	0	1	0	0	0	X2	8
0	0	0	0	0	0	0	1	0	0	0	0	X3	16
0	0	0	0	0	0	0	1	1	0	0	0	X4	24

 

As the input memory address is in decimal. 

So, Starting location (Addr = 0) for (X1, X2, X3, X4) are (0,8,16,24).

So, correct answer is C.

Answer 2

The addresses given to us are of 12 bits in length.

It is said that Chip Select is active high i.e the chip would be selected when signal to the corresponding chip would be high.

Now there is a $2:4$ decoder connected to Chip Select of the four chips.

The starting locations of the chips would be determined by first selecting the chip and  the accessing the $0^{th}$ byte of the chip.

There are four possible combinations of $I4I3$.

We would need to see the value of see the values of the last 5 bits only ($I4 \cdots I0$). As for the starting address the bits ($I11 \cdots I5$) remain 0.

$I4I3$	Resulting value ($I11 \cdots I0$)
00 ($X0$)	0 ($00000$)
01 ($X1$)	8 ($01000$)
10 ($X2$)	16 ($10000$)
11 ($X3$)	24 ($11000$)

 

The answer is hence C)

Comments

I(11) – I(5) remains zero ? How you conclude this , please help.