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Cache Memory
Recent questions tagged cache-memory
33
votes
2
answers
721
GATE CSE 2012 | Question: 54
A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ ... bit and $1$ replacement bit. The number of bits in the tag field of an address is $11$ $14$ $16$ $27$
gatecse
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in
CO and Architecture
Sep 29, 2014
by
gatecse
22.0k
views
gatecse-2012
co-and-architecture
cache-memory
normal
31
votes
3
answers
722
GATE CSE 2011 | Question: 43
An $8\text{KB}$ direct-mapped write-back cache is organized as multiple blocks, each size of $32\text{-bytes}$. The processor generates $32\text{-bit}$ addresses. The cache controller contains the tag information for each cache block comprising of the ... the cache controller to store meta-data (tags) for the cache? $4864$ bits $6144$ bits $6656$ bits $5376$ bits
go_editor
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in
CO and Architecture
Sep 29, 2014
by
go_editor
12.3k
views
gatecse-2011
co-and-architecture
cache-memory
normal
69
votes
6
answers
723
GATE CSE 2014 Set 3 | Question: 44
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write operation with a hit in cache and $10$ nanoseconds for a write ... cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.
go_editor
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in
CO and Architecture
Sep 28, 2014
by
go_editor
23.9k
views
gatecse-2014-set3
co-and-architecture
cache-memory
numerical-answers
normal
37
votes
2
answers
724
GATE CSE 2014 Set 2 | Question: 44
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected? Width of tag comparator Width of set index decoder Width of way selection multiplexer Width of processor to main memory data bus
go_editor
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in
CO and Architecture
Sep 28, 2014
by
go_editor
10.2k
views
gatecse-2014-set2
co-and-architecture
cache-memory
normal
81
votes
5
answers
725
GATE CSE 2014 Set 2 | Question: 43
In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block ... size implies a larger cache tag and hence lower cache hit time A smaller block size incurs a lower cache miss penalty
go_editor
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in
CO and Architecture
Sep 28, 2014
by
go_editor
20.9k
views
gatecse-2014-set2
co-and-architecture
cache-memory
normal
38
votes
5
answers
726
GATE CSE 2014 Set 2 | Question: 9
A $4$-way set-associative cache memory unit with a capacity of $16$ KB is built using a block size of $8$ words. The word length is $32$ bits. The size of the physical address space is $4$ GB. The number of bits for the TAG field is ____
go_editor
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in
CO and Architecture
Sep 28, 2014
by
go_editor
25.8k
views
gatecse-2014-set2
co-and-architecture
cache-memory
numerical-answers
normal
126
votes
10
answers
727
GATE CSE 2014 Set 1 | Question: 44
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$
go_editor
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in
CO and Architecture
Sep 28, 2014
by
go_editor
22.7k
views
gatecse-2014-set1
co-and-architecture
cache-memory
normal
47
votes
9
answers
728
GATE CSE 2006 | Question: 80
A CPU has a $32 KB$ direct mapped cache with $128$ byte-block size. Suppose A is two dimensional array of size $512 \times512$ with elements that occupy $8$-bytes each. Consider the following two C code segments, $P1$ and $P2$. P1: for (i=0; i<512; i++) { for (j=0; ... $P1$ be $M_{1}$and that for $P2$ be $M_{2}$. The value of $M_{1}$ is: $0$ $2048$ $16384$ $262144$
Rucha Shelke
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in
CO and Architecture
Sep 26, 2014
by
Rucha Shelke
16.7k
views
gatecse-2006
co-and-architecture
cache-memory
normal
65
votes
5
answers
729
GATE CSE 2006 | Question: 74
Consider two cache organizations. First one is $32 \; \textsf{KB}\;2\text{-way}$ set associative with $32 \; \text{byte}$ block size, the second is of same size but direct mapped. The size of an address is $32\; \text{bits}$ in both cases . A $2\text{-to-}1$ multiplexer has ... The value of $h_1$ is: $2.4 \text{ ns} $ $2.3 \text{ ns}$ $1.8 \text{ ns}$ $1.7 \text{ ns}$
Rucha Shelke
asked
in
CO and Architecture
Sep 26, 2014
by
Rucha Shelke
29.1k
views
gatecse-2006
co-and-architecture
cache-memory
normal
44
votes
4
answers
730
GATE CSE 2006 | Question: 41
A CPU has a cache with block size $64$ bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive banks with wrap-around. All the $k$ banks can be accessed in parallel, but two ... the latency of retrieving a cache block starting at address zero from main memory is: $92$ ns $104$ ns $172$ ns $184$ ns
Rucha Shelke
asked
in
CO and Architecture
Sep 26, 2014
by
Rucha Shelke
14.2k
views
gatecse-2006
co-and-architecture
cache-memory
memory-interfacing
normal
33
votes
5
answers
731
GATE CSE 1998 | Question: 18
For a set-associative Cache organization, the parameters are as follows: ... $1 \leq m \leq l$. Give the value of the hit ratio for $l = 1$.
Kathleen
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in
CO and Architecture
Sep 26, 2014
by
Kathleen
11.9k
views
gate1998
co-and-architecture
cache-memory
descriptive
28
votes
3
answers
732
GATE CSE 1999 | Question: 1.22
The main memory of a computer has $2\;\text{cm}$ blocks while the cache has $2\;\text{c}$ blocks. If the cache uses the set associative mapping scheme with $2$ blocks per set, then block $k$ of the main memory maps to the set: $(k \mod m)$ of the cache $(k \mod c)$ of the cache $(k \mod 2c)$ of the cache $(k \mod 2\; cm)$ of the cache
Kathleen
asked
in
CO and Architecture
Sep 23, 2014
by
Kathleen
7.6k
views
gate1999
co-and-architecture
cache-memory
normal
73
votes
5
answers
733
GATE CSE 2013 | Question: 20
In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are sequenced before the lines in set $(s+1)$. The main memory blocks are numbered 0 onwards. The ... $(j \text{ mod } k) * v \text{ to } (j \text{ mod } k) * v + (v-1) $
Arjun
asked
in
CO and Architecture
Sep 23, 2014
by
Arjun
14.1k
views
gatecse-2013
co-and-architecture
cache-memory
normal
24
votes
3
answers
734
GATE CSE 2005 | Question: 67
Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and the number of tag bits are respectively, $10, 17$ $10, 22$ $15, 17$ $5, 17$
Kathleen
asked
in
CO and Architecture
Sep 22, 2014
by
Kathleen
15.1k
views
gatecse-2005
co-and-architecture
cache-memory
easy
23
votes
2
answers
735
GATE CSE 2009 | Question: 29
Consider a $4$-way set associative cache (initially empty) with total $16$ cache blocks. The main memory consists of $256$ ... $3$ $8$ $129$ $216$
Kathleen
asked
in
CO and Architecture
Sep 22, 2014
by
Kathleen
14.5k
views
gatecse-2009
co-and-architecture
cache-memory
normal
93
votes
10
answers
736
GATE CSE 2007 | Question: 80
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in the system. A $50 \times 50$ two-dimensional array of bytes is stored in the main ... data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$
Kathleen
asked
in
CO and Architecture
Sep 21, 2014
by
Kathleen
32.4k
views
gatecse-2007
co-and-architecture
cache-memory
normal
22
votes
1
answer
737
GATE CSE 2007 | Question: 10
Consider a $4$-way set associative cache consisting of $128$ lines with a line size of $64$ words. The CPU generates a $20-bit$ address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively: $9, 6, 5$ $7, 7, 6$ $7, 5, 8$ $9, 5, 6$
Kathleen
asked
in
CO and Architecture
Sep 21, 2014
by
Kathleen
13.1k
views
gatecse-2007
co-and-architecture
cache-memory
normal
17
votes
3
answers
738
GATE CSE 2004 | Question: 65
Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is: $8, 12, 0, 12, 8$. $2$ $3$ $4$ $5$
Kathleen
asked
in
CO and Architecture
Sep 18, 2014
by
Kathleen
15.2k
views
gatecse-2004
co-and-architecture
cache-memory
normal
34
votes
1
answer
739
GATE CSE 2002 | Question: 10
In a C program, an array is declared as $\text{float} \ A[2048]$. Each array element is $4 \ \text{Bytes}$ in size, and the starting address of the array is $0x00000000$. This program is run on a computer that has a direct ... ? Justify your answer briefly. Assume that the data cache is initially empty and that no other data or instruction accesses are to be considered.
Kathleen
asked
in
CO and Architecture
Sep 15, 2014
by
Kathleen
6.2k
views
gatecse-2002
co-and-architecture
cache-memory
normal
descriptive
29
votes
2
answers
740
GATE CSE 2001 | Question: 9
A CPU has $32-bit$ memory address and a $256 \ KB$ cache memory. The cache is organized as a $4-way$ set associative cache with cache block size of $16$ bytes. What is the number of sets in the cache? What is the size (in bits) of ... are required to find the byte offset within a cache block? What is the total amount of extra memory (in bytes) required for the tag bits?
Kathleen
asked
in
CO and Architecture
Sep 14, 2014
by
Kathleen
13.0k
views
gatecse-2001
co-and-architecture
cache-memory
normal
descriptive
44
votes
5
answers
741
GATE CSE 2001 | Question: 1.7, ISRO2008-18
More than one word are put in one cache block to: exploit the temporal locality of reference in a program exploit the spatial locality of reference in a program reduce the miss penalty none of the above
Kathleen
asked
in
CO and Architecture
Sep 14, 2014
by
Kathleen
17.0k
views
gatecse-2001
co-and-architecture
easy
cache-memory
isro2008
45
votes
4
answers
742
GATE CSE 1992 | Question: 5-a
The access times of the main memory and the Cache memory, in a computer system, are $500$ n sec and $50$ nsec, respectively. It is estimated that $80\%$ of the main memory request are for read the rest for write. The hit ratio for ... policy (where both main and cache memories are updated simultaneously) is used. Determine the average time of the main memory (in ns).
Kathleen
asked
in
CO and Architecture
Sep 13, 2014
by
Kathleen
24.0k
views
gate1992
co-and-architecture
cache-memory
normal
numerical-answers
61
votes
4
answers
743
GATE CSE 2008 | Question: 71
Consider a machine with a $2$-way set associative data cache of size $64\text{Kbytes}$ and block size $16\text{bytes}$. The cache is managed using $32\;\text{bit}$ virtual addresses and the page size is $4\text{Kbytes}$. A program to be run on this ... total size of the tags in the cache directory is: $32\text{Kbits}$ $34\text{Kbits}$ $64\text{Kbits}$ $68\text{Kbits}$
Kathleen
asked
in
CO and Architecture
Sep 12, 2014
by
Kathleen
18.7k
views
gatecse-2008
co-and-architecture
cache-memory
normal
61
votes
3
answers
744
GATE CSE 2008 | Question: 35
For inclusion to hold between two cache levels $L_1$ and $L_2$ in a multi-level cache hierarchy, which of the following are necessary? $L_1$ must be write-through cache $L_2$ must be a write-through cache The associativity of $L_2$ must be greater than that of $L_1$ The ... be at least as large as the $L_1$ cache IV only I and IV only I, II and IV only I, II, III and IV
Kathleen
asked
in
CO and Architecture
Sep 12, 2014
by
Kathleen
24.5k
views
gatecse-2008
co-and-architecture
cache-memory
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