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Recent questions tagged circuit-output
21
votes
4
answers
91
GATE CSE 2005 | Question: 15
Consider the following circuit. Which one of the following is TRUE? $f$ is independent of $x$ $f$ is independent of $y$ $f$ is independent of $z$ None of $x, y, z$ is redundant
Kathleen
asked
in
Digital Logic
Sep 22, 2014
by
Kathleen
8.5k
views
gatecse-2005
digital-logic
circuit-output
normal
33
votes
7
answers
92
GATE CSE 2006 | Question: 37
Consider the circuit in the diagram. The $\oplus$ operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared). The following data: $100110000$ is supplied to the “data” terminal in nine clock cycles. After that the values of $q_{2}q_{1}q_{0}$ are: $000$ $001$ $010$ $101$
Rucha Shelke
asked
in
Digital Logic
Sep 22, 2014
by
Rucha Shelke
15.7k
views
gatecse-2006
digital-logic
circuit-output
easy
34
votes
2
answers
93
GATE CSE 2006 | Question: 35
Consider the circuit above. Which one of the following options correctly represents $f\left(x,y,z\right)$ $x\bar{z}+xy+\bar{y}z$ $x\bar{z}+xy+\overline{yz}$ $xz+xy+\overline{yz}$ $xz+x\bar{y}+\bar{y}z$
Rucha Shelke
asked
in
Digital Logic
Sep 22, 2014
by
Rucha Shelke
9.7k
views
gatecse-2006
digital-logic
circuit-output
normal
66
votes
6
answers
94
GATE CSE 2007 | Question: 36
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ ... through the following sequence: $0, 3, 4$ $0, 3, 4, 5$ $0, 1, 2, 3, 4$ $0, 1, 2, 3, 4, 5$
Kathleen
asked
in
Digital Logic
Sep 21, 2014
by
Kathleen
19.3k
views
gatecse-2007
digital-logic
circuit-output
normal
44
votes
5
answers
95
GATE CSE 2004 | Question: 61
Consider the partial implementation of a $2-bit$ counter using $T$ flip-flops following the sequence $0-2-3-1-0,$ as shown below. To complete the circuit, the input $X$ should be $Q_2^c$ $Q_2 + Q_1$ $\left(Q_1 + Q_2\right)^c$ $Q_1 \oplus Q_2$
Kathleen
asked
in
Digital Logic
Sep 18, 2014
by
Kathleen
19.1k
views
gatecse-2004
digital-logic
circuit-output
normal
70
votes
5
answers
96
GATE CSE 2006 | Question: 8
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?
Rucha Shelke
asked
in
Digital Logic
Sep 16, 2014
by
Rucha Shelke
18.6k
views
gatecse-2006
digital-logic
normal
circuit-output
39
votes
2
answers
97
GATE CSE 2002 | Question: 2.2
Consider the following multiplexer where $I0, I1, I2, I3$ are four data input lines selected by two address line combinations $A1A0=00,01,10,11$ respectively and $f$ is the output of the multiplexor. EN is the Enable input. The function $f(x,y,z)$ implemented by the above circuit is $xyz'$ $xy + z$ $x + y$ None of the above
Kathleen
asked
in
Digital Logic
Sep 15, 2014
by
Kathleen
13.3k
views
gatecse-2002
digital-logic
circuit-output
normal
57
votes
4
answers
98
GATE CSE 2002 | Question: 2-1
Consider the following logic circuit whose inputs are functions $f_1, f_2, f_3$ and output is $f$ Given that $f_1(x,y,z) = \Sigma (0,1,3,5)$ $f_2(x,y,z) = \Sigma (6,7),$ and $f(x,y,z) = \Sigma (1,4,5).$ $f_3$ is $\Sigma (1,4,5)$ $\Sigma (6,7)$ $\Sigma (0,1,3,5)$ None of the above
Kathleen
asked
in
Digital Logic
Sep 15, 2014
by
Kathleen
14.3k
views
gatecse-2002
digital-logic
normal
canonical-normal-form
circuit-output
62
votes
5
answers
99
GATE CSE 2001 | Question: 2.8
Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$ Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?
Kathleen
asked
in
Digital Logic
Sep 14, 2014
by
Kathleen
21.4k
views
gatecse-2001
digital-logic
circuit-output
normal
37
votes
5
answers
100
GATE CSE 2000 | Question: 2.12
The following arrangement of master-slave flip flops has the initial state of $P, Q$ as $0, 1$ (respectively). After three clock cycles the output state $P, Q$ is (respectively), $1, 0$ $1, 1$ $0, 0$ $0, 1$
Kathleen
asked
in
Digital Logic
Sep 14, 2014
by
Kathleen
11.5k
views
gatecse-2000
digital-logic
circuit-output
normal
flip-flop
27
votes
1
answer
101
GATE CSE 1991 | Question: 5-a
Analyse the circuit in Fig below and complete the following table ${\begin{array}{|c|c|c|}\hline \textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline 0&0\\\ 0&1 \\ 1&0 \\ 1&1 \\ \hline \end{array}}$
Kathleen
asked
in
Digital Logic
Sep 12, 2014
by
Kathleen
3.9k
views
gate1991
digital-logic
normal
circuit-output
sequential-circuit
descriptive
3
votes
1
answer
102
GATE CSE 1991 | Question: 01,i
Kathleen
asked
in
Others
Sep 11, 2014
by
Kathleen
1.1k
views
gate1991
digital-logic
circuit-output
normal
out-of-gate-syllabus
58
votes
3
answers
103
GATE CSE 2005 | Question: 62
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let $A_{i}$ represents the logic level on the line $A$ in the $i$-th clock period. Let $A'$ represent the complement of $A$. The correct output sequence on $Y$ over the ... $A_{1} A_{2}' A_{3} A_{4} A_{5}'$
Isha Karn
asked
in
Digital Logic
Sep 3, 2014
by
Isha Karn
17.0k
views
gatecse-2005
digital-logic
circuit-output
normal
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