MadeEasy Subject Test: CO & Architecture - Pipelining

Question

Consider a pipelined processor with 5 stages (IF) Instruction Fetch , (ID) Instruction Decode and operand fetch, (PO) Perform Operation, (MA) Data Memory Access, (WB) Write Back. The IF, ID, MA and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 cycle for ADD and SUB instructions and takes 3 clock cycles for MUL instruction respectively. Operand forwarding from PO to ID and WB to ID )is used in the pipeline. The maximum number of stalls presents for any instruction in execution of following sequence of instruction is___________.

Comments

calculate entire table it is looks like

CYCLES

1

2

3

4

5

6

7

8

9

10

11

12

WA

I0

I1

I2

I3

I4

MA

I0

I1

I2

I3

I4

PO

I0

I1

I2

I3

I3

I3

I4

ID

I0

I1

I2

I3

I4

///

///

IF

I0

I1

I2

I3

I4

//// ARE INDICATES STALLS.

---

For ideal pipelining, In every cycle, one instruction should be completed. (Ignoring the first instruction). But because PO phase takes different no. of cycles for different kind of instructions, it is not possible.

Even ever we encounter multiply instruction it will take 3 cycles to complete its execution, Ideally it should take one instruction. So no. of stalls is 3 - 1 = 2 stalls.

Informally, A stall is when we have finished our work on a stage and we want to move the next stage but as next stage is occupied (not free yet) we are not able to do so.

---

2 stall

Answer 1

R2 <--  R0+R1

R1 <-- R2-R1

R0 <-- R2-R0

R2 <-- R1*R0

R3 <--R1+R0

I/C	1	2	3	4	5	6	7	8	9	10	11
I0	IF	ID	PO	MA	WB
I1		IF	ID	PO	MA	WB
I2			IF	ID	PO	MA	WB
I3				IF	ID	PO	PO	PO	MA	WB
I4					IF	ID	X	X	PO	MA	WB

In this instruction Pipeline X represent the Stall.

Hence Maximum no. of Stall = 2.

Comments

In the question , it is mentioned that operand forwarding​ is used from PO->ID and WB->ID.

Can anyone​ explain how this technique is used in this question to determine the required answer?

---

Yes

We can not perfome operand forwading from po to id

---

@sushmita

In 4h clock I2 is reading wrong value of R2 because value of R2 is written to register file in 5th clock by I1

How I2 will get correct value of R2 then ...