in CO and Architecture edited by
15,072 views
24 votes
24 votes

Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and the number of tag bits are respectively,

  1. $10, 17$
  2. $10, 22$
  3. $15, 17$
  4. $5, 17$
in CO and Architecture edited by
15.1k views

3 Answers

38 votes
38 votes
Best answer

Number of blocks $= \dfrac{\text{cache size}}{\text{block size}}= \dfrac{32\text{-KB}}{32}=\text{1024-Bytes.}$

So, indexing requires $\text{10-bits}.$ Number of OFFSET bits required to access $\text{32-bit block} = 5.$
So, number of TAG bits $= 32 - 10 - 5 = 17.$

So, answer is (A).

edited by
by

4 Comments

I have the same doubt as Sachin's. We usually do these calculations on physical address.
2
2
why not c ....????
0
0
guys cache indexing means ‘ability to point out a line in cache’ no of lines in cache are 1024 hence we only need 10 bits in it not 15 (ie we dont include word offset)
1
1
7 votes
7 votes

In Direct mapped cache:

    Address format= Tag + cache index + Offset

     Offset  = log(block size)  = log(32B) = log(2^5) =5 bits

     index = log(cache size / block size) = log(32KB)/log(32B) = 10 bits

     Finally Tag = Total bits - index - offset = 32 - 10 - 5 = 17 bits

NOTE: Base of log is 2 

2 votes
2 votes

.......……….............………..........…….……………..

Answer:

Related questions