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CO and Architecture: Avg stall cycles per instruction
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8 votes

Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache to memory is $100$ cycles. The hit time of $L_{2}$ cache is $20$ cycle. The hit time of $L_{1}$ cache is $10$ cycles. If there are $2.5$ memory references per instruction. How many average stall cycle per instruction?

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4 Answers

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6 votes

To calculate stall cycles:there are total 500 references to L1.50 are miss in L1. it means that if we would have been lucky we would have got them( 50 references) in L1 only.but they were a miss so we have to go to L2 .Hence this is the stall time or extra time.

so for 30 references out of 50 we need to go till L2. So extra time is 20 clock cycles.

for 20 references out of 50 we need to go till main mem . so extra time is (20cc+100cc)=120 cc.

Rest u can understand from the snap :)

Hope it helps :)

edited by
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3 votes
No of stalls for 500 memory references=$50*20+20*100=3000$

$2.5$ memory references = $1$ instruction

$\therefore500$ memory references= $200$ instructions

$\therefore$ Average Stalls/Instruction=$\frac{3000}{200}=15$
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0 votes
Avg Access time= (10 +.1*10+.1*.4*100 )*2.5 Cycles. Stall is when reference doesn't  hit in cache 1 and it occurs (.1*10+.1*.4*100) times so stall cycles will be (.1*10+.1*.4*100)*2.5 = 15 cycles.
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0 votes
Stall cycle created due to  some miss happen in cache and CPU need to access memory

In this question we can see ,

there are $50$ misses in $L_{1}$ cache for which we need to access $L_{2}.$

In $L_{2}$ there are $30$ hits, but again for $200$ misses we need to access Main Memory.

So, total stall cycles are $30*20+20*(20+100)=3000$ stall cycles

Now,

for $500$ memory reference  , there are $3000$ stall cycles.

for $1$ memory reference  , there are $3000/500$ stall cycles.

Here, each instruction needs $2.5$ memory reference.

So, for $2.5$ memory reference  , there are $(3000/500)*2.5=15$ stall cycles or $15 stall/instruction$

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