GATE CSE 2011 | Question: 28

Question

On a non-pipelined sequential processor, a program segment, which is the part of the interrupt service routine, is given to transfer $500$ bytes from an I/O device to memory.

        Initialize the address register
        Initialize the count to 500
LOOP:   Load a byte from device              
        Store in memory at address given by address register
        Increment the address register
        Decrement the count
        If count !=0 go to LOOP

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires $20$ clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

What is the approximate speed up when the DMA controller based design is used in a place of the interrupt driven program based input-output?

• A. $3.4$
• B. $4.4$
• C. $5.1$
• D. $6.7$

Comments

https://www.youtube.com/watch?v=TbtZTuJMS04

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AGAIN NPTEL ASSIGNMENT QUESTION

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Nptel put the gate question in assignment and not vice-versa.

The assignment is of2017 and question is of gate-2011

Answer 1

$$\begin{array}{llc} & \textbf{Statement} & \textbf{Clock Cycles(s) Needed} \\\hline
& \text{Initialize the address register} & \text{1} \\
& \text{Initialize the count to 500} & \text{1} \\
\text{LOOP:} &\textbf{Load}\text{ a byte from device} & \text{2}  \\
& \textbf{Store}\text{ in memory at address given by address register} & \text{2} \\
& \text{Increment the address register} & \text{1} \\ & \text{Decrement the count} & \text{1} \\
& \text{If count != 0 go to LOOP} & \text{1}  \end{array}$$
Interrupt driven transfer time $= 1+1+500\times(2+2+1+1+1) = 3502$

DMA based transfer time $= 20+500\times 2 = 1020$

Speedup $= 3502/1020 = 3.4$

Correct Answer: $A$

Comments

If count != 0 go to LOOP # will execute 501 times and total will be 3503 for ISR based approach. Though this doesn't affect the answer.

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No..loop runs for 500 times only..

Take count=3 .and check it runs for 3 times only..

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Could someone tel how are the DMA transfer time calculated ?

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@ PEKKA 

 how are the DMA transfer time calculated ?

See in question it says The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

So DMA transfer time = 20 ( this is total nuber of clock cycles for initialization ) + 500 * 2 ( as loop will go up to 500 times as a device to memory transfer and each transfer takes 2 clock cycles ) 

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How interrupt driven time is calculated ?

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@Bikram sir

Here in interrupt driven transfer ...is interrupt overhead happening after loading every single byte as happens in interrrupt driven i/o ..here once interrupt generated bytes are loaded in loop one after the other..isn't this a interrupt driven i/o where each word tranfer causes interrrupt ?

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@Manu Thakur Sir, @srestha Ma'am @jatin khachane 1here why we have not taken DMA overhead at the end of transfer,

as DMA before the start it takes times to LOAD MAR and count resgister, then transfer bulk of data , then interrupt the processor about transfer,

20 clock cycle at the end of transfer we need to take? 

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here why we have not taken DMA overhead at the end of transfer,

It has been taken. Check 20 c.c. nothing but DMA overhead. Isnot it? 

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@srestha  Ma'am, 

In the calculation of DMA transfer time, why is the time required for,  Increment the address register, to decrement the count, and If count != 0 go to LOOP not considered? 

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That program has to be given for  transfer I/O to memory, but for DMA they used alternative approach.

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Oh so in this DMA approach we don't need to increment the register or those other instructions or in other words in the DMA approach it uses 500 iterations of 2 cycles each to transfer those 500 bytes plus the 20 cycles for initialisation, am I right ?

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yes, exactly.

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Thank you, that has cleared up my doubt.

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Such a beautiful question OMG