Branch Stall

Question

What does the Following line states:- 

Branch instruction aren't overlapped i.e. the instruction after the branch is not fetched till the branch instruction is executed.

Say in below Question :-    

An instruction pipeline has Five Stages where each stage takes 2ns and all instruction use all five stages.Branch instruction aren't overlapped i.e. the instruction after the branch is not fetched till the branch instruction is executed.

How many stalls will be there?

Will it be 4.According to my understanding before fetching the branch target the branch instruction will be completely executed hence since its a five stage pipeline then when the branch instruction will be at final stage before fetching the branch target the instruction which was incorrectly fetched will be in stage 4. Hence total 4 Stalls isn't it?

Comments

If the 5 stages are like IF,ID,EX,MEM & WB and given Branch instruction aren't overlapped i.e. the instruction after the branch is not fetched till the branch instruction is executed, then there will be stalls for ID & EX and so, 3 cycles will be considered for branch instruction. {next instruction will be fetched at the end of EX, i.e., at MEM}

correct me if i'm wrong!

---

You can see a similar question where all cases of Branch Stalling is given in the answer.

https://gateoverflow.in/212840/pipeline-stall