digital

Question

 

 

THE ABOVE CIRCUIT IS A  MODULUS ______________  COUNTER ????

 

Comments

hey don't post the answer please

only post the question..if anyone ask what's the correct answer then tell them

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I removed the answer.

Can u explain pls

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Note that  when  Q1 = 1   Q3 = 1 and Q2 = 0  then ( NAND gate o/p = 0 ) that means  it's going to RESET the counter

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CLR is used to turn all flipflps to 0

therefore , 1 0 1 0 is not stable

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@Magma

What does a stable state mean?

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It's a mod 10 asynchronous counter, where 1 0 1 0 is unstable state. Why?

Q3 Q2 Q1 Q0

0 0 0 0

0 0 0 1

...

...

1 0 0 1

1 0 1 0 - This unstable because whenever output will be equal to  1 0 1 0, like usual output will be passed to NAND gates. Q1 Nand Q3 gives result 0. Q2 Nand Q3 gives 1, hence 0 Nand 1 gives 1, and then self Nand gives 0, now this output is connected to clr implies it will clear all states to 0 0 0 0 quickly. Hence as soon as we get 1 0 1 0 it will get quickly transform to  0 0 0 0 hence it is unstable. This also implies we are dealing with mod 10 counter as we can get all stable counter values from 0 to 9.

A stable state means - counter value remains same after output is generated. for all values from 0 to 9, when you pass output of those states to Nand gates in the end 1 is generated which keeps the counter value same, but whenever 0 input is provided to clr (in case of 1 0 1 0) it resets all counter value to 0.

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actually earliar i saw the wrong solution,

its not a mod 9 counter ; its a mod 10 counter

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I calculated that I got mod 9. If mod 10 is the answer then somebody please explain it.

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actually your answer is correct @swapnil naik; u just need to edit it!

u are gettting states from 0-9,so how can it be a mod 9 counter,

It should be a mod 10 counter right?

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Yeah, sorry my mistake I failed to remember that point. Thanks. It's a mod 10 counter.

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how are the flip flops producing outputs over here?

 i am confused as they are negative edge triggered flip flops?

pls explain @Swapnil Naik

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Yes they are negative edge triggered flip-flop.

 

Look at them vertically from down to top you will get output sequence. Observe those negative edges where output changes. I hope your doubt is clear now.

https://www.allaboutcircuits.com/textbook/digital/chpt-11/asynchronous-counters/

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pls tell me one thing!

i am really confused, when i evaluated that NAND expression which is going to CLR of all the flip flops ,

i got it as

Q3' + Q1'Q2'

now what i have read till now is that whenever the input to CLR is 1, it works means it CLEARS ALL THE STATES AND COMES TO 0000.

and u all have made it worked when CLR is 0, right.

according to the expression which i got, am getting 1 on all the inputs 0000 to 1001, and getting 0 on 1010.

pls tell me where am going wrong @Swapnil Naik 

 

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Look at them vertically from down to top you will get output sequence. Observe those negative edges where output changes. I hope your doubt is clear now

Tell me one thing @Swapnil Naik, why only bottom to top, i know that Q3 is the MSB and Q0 is the LSB, but i have seen many questions in which this concept is not taken into consideration.

so how will i get to know where to apply this and where not to apply this???

i thought the input is first given to Q0 and it is going from Q0 to Q1 and so on , so it should be taken like Q0Q1Q2Q3,

??

PLS RESOLVE BOTH OF MY DOUBTS! AM REALLY CONFUSED!!

 

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Answer to your first query, don't evaluate expression of Nand gate, putting values or little solving is sufficient. When input of clr is low(0), it will reset all output to 0. Sometimes they give clr complement in diagram that time one may require to take care, here it is just clr.

This types of question are easy to solve and practice is necessary.

https://www.quora.com/What-is-function-preset-and-clear-in-J-K-flip-flop

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Usually in counters we consider Q3Q2Q1Q0 in reverse order to get required output. A counter goes from 0,1,2,3,...

but if you consider it Q0Q1Q2Q3 you will get output state as 8,4,12... it won't be valid as a counter output. You can always arrange circuit in required format.

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i think here it is clr complement 

see this example

https://gateoverflow.in/1234/gate2007-36

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There they have clearly mentioned when clr is 1, it clears output to 0. In our case we don't have such information, the first thing that struck me when I trying to solve this problem we get clr 1 from state 0,1 .... and if I assume it will clear all output to 0 0 0 0 then, how my counter will increment hence the first thought was it is reversed, so I assumed that whenever it will be 0 it will reset input.

at 1 0 1 0 you get output from last Nand as zero and hence you reset the all output to 0 0 0 0. Sometimes it is difficult to recollect what we have learned, but then solving question logically should give you the right answer. When they give when clr is 1 then reset then no problem, when they don't mention anything assume it will reset at 0. In that question that might be a clr complement.

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yes ,u are right!