no of clock cycle required for bellow figure "in case of no operand forwarding used" ??

Question

Comments

Why from Instruction 2 onwards, the Decode is given in RED?

 What does it mean?

Answer 1

In case of no operand forwarding

12 cycles are required. Id stage get operand after WB..

Comments

top one

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what kind of structural dependency u r adding between 4 th and 5 th instruction???

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Answer should be 11 and if option 11 is not there- then only consider other options.

Answer 2

Nothing given, am considering risc pipelining. Data Mem accessed during MA stage only. It will take 11 cycles 

Comments

Plz explain, why Instruction 2 onwards ,everyone is waiting 2 clock cycles before Instruction Decode?

Answer 3

IF     ID     EX    MEM     WB

        IF                                        ID        EX      MEM      WB

                  IF                                           ID        EX          MEM       WB

                           IF                                               ID            EX          MEM       WB

                                          IF                                                  ID             EX         MEM        WB

 

Without operand forwarding there would be 12 cycles

Comments

Unless mentioned so not consider structural hazard. Because usually Instruction comes from Instruction cache and data from data cache and there is no structural hazard with respect to instruction fetch. Long back there was and hence such questions.

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Arjun should we do instruction decode in last stage ie wb of previous one or after that(if operand req is dependent)

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Plz explain, why Instruction 2 onwards ,everyone is waiting 2 clock cycles before Instruction Decode?