How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.
@Priyanka Agarwal No!
Decode Stage: During this stage the encoded instruction present in the instruction register is interpreted by the decoder.
2 Memory references are required here.
It is Basically an Indirect Addressing Mode.
EA= [Address Field Value] → [Reg. name (R3)] → [Data (Operand)]
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